^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * hwmon-vid.c - VID/VRM/VRD voltage conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Partly imported from i2c-vid.h of the lm_sensors project
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * With assistance from Trent Piepho <xyzzy@speakeasy.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hwmon-vid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Common code for decoding VID pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * available at http://developer.intel.com/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * For VRD 10.0 and up, "VRD x.y Design Guide",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * available at http://developer.intel.com/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * http://support.amd.com/us/Processor_TechDocs/26094.PDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Table 74. VID Code Voltages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This corresponds to an arbitrary VRM code of 24 in the functions below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * These CPU models (K8 revision <= E) have 5 VID pins. See also:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * AMD NPT Family 0Fh Processors, AMD Publication 32559,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Table 71. VID Code Voltages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This corresponds to an arbitrary VRM code of 25 in the functions below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * These CPU models (K8 revision >= F) have 6 VID pins. See also:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The 17 specification is in fact Intel Mobile Voltage Positioning -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * (IMVP-II). You can find more information in the datasheet of Max1718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * The 13 specification corresponds to the Intel Pentium M series. There
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * doesn't seem to be any named specification for these. The conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * tables are detailed directly in the various Pentium M datasheets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * https://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * The 14 specification corresponds to Intel Core series. There
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * doesn't seem to be any named specification for these. The conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * tables are detailed directly in the various Pentium Core datasheets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * https://www.intel.com/design/mobile/datashts/309221.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * The 110 (VRM 11) specification corresponds to Intel Conroe based series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * https://www.intel.com/design/processor/applnots/313214.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * vrm is the VRM/VRD document version multiplied by 10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * val is the 4-bit or more VID code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Returned value is in mV to avoid floating point in the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Some VID have some bits in uV scale, this is rounded to mV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int vid_from_reg(int val, u8 vrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) switch (vrm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case 100: /* VRD 10.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* compute in uV, round to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if ((val & 0x1f) == 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if ((val & 0x1f) <= 0x09 || val == 0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) vid = 1087500 - (val & 0x1f) * 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) vid = 1862500 - (val & 0x1f) * 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (val & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) vid -= 12500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return (vid + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 110: /* Intel Conroe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* compute in uV, round to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (val < 0x02 || val > 0xb2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return (1600000 - (val - 2) * 6250 + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 24: /* Athlon64 & Opteron */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (val == 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case 25: /* AMD NPT 0Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return (val < 32) ? 1550 - 25 * val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) : 775 - (25 * (val - 31)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 26: /* AMD family 10h to 15h, serial VID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (val >= 0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return DIV_ROUND_CLOSEST(15500 - 125 * val, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case 91: /* VRM 9.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case 90: /* VRM 9.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return val == 0x1f ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 1850 - val * 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case 85: /* VRM 8.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return (val & 0x10 ? 25 : 0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ((val & 0x0f) > 0x04 ? 2050 : 1250) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ((val & 0x0f) * 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 84: /* VRM 8.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 82: /* VRM 8.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return val == 0x1f ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val & 0x10 ? 5100 - (val) * 100 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 2050 - (val) * 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case 17: /* Intel IMVP-II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return val & 0x10 ? 975 - (val & 0xF) * 25 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 1750 - val * 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case 131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Exception for Eden ULV 500 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (vrm == 131 && val == 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 1708 - val * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case 14: /* Intel Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* compute in uV, round to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) default: /* report 0 for unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (vrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_warn("Requested unsupported VRM version (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (unsigned int)vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL(vid_from_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * After this point is the code to automatically determine which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * VRM/VRD specification should be used depending on the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct vrm_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 model_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 model_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 stepping_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 vrm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ANY 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * The stepping_to parameter is highest acceptable stepping for current line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * The model match must be exact for 4-bit values. For model values 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * and above (extended model), all models below the parameter will match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct vrm_model vrm_models[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {X86_VENDOR_AMD, 0x6, 0x0, ANY, ANY, 90}, /* Athlon Duron etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {X86_VENDOR_AMD, 0xF, 0x0, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * In theory, all NPT family 0Fh processors have 6 VID pins and should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * thus use vrm 25, however in practice not all mainboards route the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * 6th VID pin because it is never needed. So we use the 5 VID pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * variant (vrm 24) for the models which exist today.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {X86_VENDOR_AMD, 0xF, 0x40, 0x7F, ANY, 24}, /* NPT family 0Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {X86_VENDOR_AMD, 0xF, 0x80, ANY, ANY, 25}, /* future fam. 0Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {X86_VENDOR_AMD, 0x10, 0x0, ANY, ANY, 25}, /* NPT family 10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {X86_VENDOR_AMD, 0x11, 0x0, ANY, ANY, 26}, /* family 11h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {X86_VENDOR_AMD, 0x12, 0x0, ANY, ANY, 26}, /* family 12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {X86_VENDOR_AMD, 0x14, 0x0, ANY, ANY, 26}, /* family 14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {X86_VENDOR_AMD, 0x15, 0x0, ANY, ANY, 26}, /* family 15h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {X86_VENDOR_INTEL, 0x6, 0x0, 0x6, ANY, 82}, /* Pentium Pro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Pentium II, Xeon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Mobile Pentium,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Celeron */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {X86_VENDOR_INTEL, 0x6, 0x7, 0x7, ANY, 84}, /* Pentium III, Xeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {X86_VENDOR_INTEL, 0x6, 0x8, 0x8, ANY, 82}, /* Pentium III, Xeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {X86_VENDOR_INTEL, 0x6, 0x9, 0x9, ANY, 13}, /* Pentium M (130 nm) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {X86_VENDOR_INTEL, 0x6, 0xA, 0xA, ANY, 82}, /* Pentium III Xeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {X86_VENDOR_INTEL, 0x6, 0xB, 0xB, ANY, 85}, /* Tualatin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {X86_VENDOR_INTEL, 0x6, 0xD, 0xD, ANY, 13}, /* Pentium M (90 nm) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {X86_VENDOR_INTEL, 0x6, 0xE, 0xE, ANY, 14}, /* Intel Core (65 nm) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {X86_VENDOR_INTEL, 0x6, 0xF, ANY, ANY, 110}, /* Intel Conroe and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {X86_VENDOR_INTEL, 0xF, 0x0, 0x0, ANY, 90}, /* P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {X86_VENDOR_INTEL, 0xF, 0x1, 0x1, ANY, 90}, /* P4 Willamette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {X86_VENDOR_INTEL, 0xF, 0x2, 0x2, ANY, 90}, /* P4 Northwood */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {X86_VENDOR_INTEL, 0xF, 0x3, ANY, ANY, 100}, /* Prescott and above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * assume VRD 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {X86_VENDOR_CENTAUR, 0x6, 0x7, 0x7, ANY, 85}, /* Eden ESP/Ezra */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x8, 0x7, 85}, /* Ezra T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, 0x7, 85}, /* Nehemiah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, ANY, 17}, /* C3-M, Eden-N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, 0x7, 0}, /* No information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, ANY, 13}, /* C7-M, C7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Eden (Esther) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {X86_VENDOR_CENTAUR, 0x6, 0xD, 0xD, ANY, 134}, /* C7-D, C7-M, C7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Eden (Esther) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Special case for VIA model D: there are two different possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * VID tables, so we have to figure out first, which one must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * used. This resolves temporary drm value 134 to 14 (Intel Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 7-bit VID), 13 (Pentium M 6-bit VID) or 131 (Pentium M 6-bit VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * + quirk for Eden ULV 500 MHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Note: something similar might be needed for model A, I'm not sure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static u8 get_via_model_d_vrm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int vid, brand, __maybe_unused dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const char *brands[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "C7-M", "C7", "Eden", "C7-D"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rdmsr(0x198, dummy, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vid &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rdmsr(0x1154, brand, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) brand = ((brand >> 4) ^ (brand >> 2)) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (vid > 0x3f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_info("Using %d-bit VID table for VIA %s CPU\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 7, brands[brand]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_info("Using %d-bit VID table for VIA %s CPU\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 6, brands[brand]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Enable quirk for Eden */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return brand == 2 ? 131 : 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static u8 find_vrm(u8 family, u8 model, u8 stepping, u8 vendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) for (i = 0; i < ARRAY_SIZE(vrm_models); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (vendor == vrm_models[i].vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) family == vrm_models[i].family &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) model >= vrm_models[i].model_from &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) model <= vrm_models[i].model_to &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) stepping <= vrm_models[i].stepping_to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return vrm_models[i].vrm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 vid_which_vrm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct cpuinfo_x86 *c = &cpu_data(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 vrm_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (c->x86 < 6) /* Any CPU with family lower than 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0; /* doesn't have VID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_stepping, c->x86_vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (vrm_ret == 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) vrm_ret = get_via_model_d_vrm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (vrm_ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pr_info("Unknown VRM version of your x86 CPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return vrm_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* and now for something completely different for the non-x86 world */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 vid_which_vrm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pr_info("Unknown VRM version of your CPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) EXPORT_SYMBOL(vid_which_vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_DESCRIPTION("hwmon-vid driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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