^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2011 Hans de Goede <hdegoede@redhat.com> *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRVNAME "f71882fg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIO_F71858FG_LD_HWM 0x02 /* Hardware monitor logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIO_F71882FG_LD_HWM 0x04 /* Hardware monitor logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIO_REG_LDSEL 0x07 /* Logical device select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIO_REG_DEVREV 0x22 /* Device revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIO_REG_ENABLE 0x30 /* Logical device enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIO_F71808E_ID 0x0901 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIO_F71808A_ID 0x1001 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIO_F71858_ID 0x0507 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIO_F71862_ID 0x0601 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SIO_F71868_ID 0x1106 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SIO_F71869_ID 0x0814 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SIO_F71869A_ID 0x1007 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIO_F71882_ID 0x0541 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SIO_F71889_ID 0x0723 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SIO_F71889E_ID 0x0909 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SIO_F71889A_ID 0x1005 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SIO_F8000_ID 0x0581 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SIO_F81768D_ID 0x1210 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SIO_F81865_ID 0x0704 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SIO_F81866_ID 0x1010 /* Chipset ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REGION_LENGTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADDR_REG_OFFSET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DATA_REG_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define F71882FG_REG_IN_STATUS 0x12 /* f7188x only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define F71882FG_REG_IN_BEEP 0x13 /* f7188x only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define F71882FG_REG_IN(nr) (0x20 + (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define F71882FG_REG_IN1_HIGH 0x32 /* f7188x only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define F81866_REG_IN_STATUS 0x16 /* F81866 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define F81866_REG_IN_BEEP 0x17 /* F81866 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define F81866_REG_IN1_HIGH 0x3a /* F81866 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define F71882FG_REG_FAN(nr) (0xA0 + (16 * (nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define F71882FG_REG_FAN_TARGET(nr) (0xA2 + (16 * (nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define F71882FG_REG_FAN_FULL_SPEED(nr) (0xA4 + (16 * (nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define F71882FG_REG_FAN_STATUS 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define F71882FG_REG_FAN_BEEP 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define F71882FG_REG_TEMP(nr) (0x70 + 2 * (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define F71882FG_REG_TEMP_OVT(nr) (0x80 + 2 * (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define F71882FG_REG_TEMP_HIGH(nr) (0x81 + 2 * (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define F71882FG_REG_TEMP_STATUS 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define F71882FG_REG_TEMP_BEEP 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define F71882FG_REG_TEMP_CONFIG 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define F71882FG_REG_TEMP_HYST(nr) (0x6C + (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define F71882FG_REG_TEMP_TYPE 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define F71882FG_REG_TEMP_DIODE_OPEN 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define F71882FG_REG_PWM(nr) (0xA3 + (16 * (nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define F71882FG_REG_PWM_TYPE 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define F71882FG_REG_PWM_ENABLE 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define F71882FG_REG_FAN_HYST(nr) (0x98 + (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define F71882FG_REG_FAN_FAULT_T 0x9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define F71882FG_FAN_NEG_TEMP_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define F71882FG_FAN_PROG_SEL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define F71882FG_REG_POINT_PWM(pwm, point) (0xAA + (point) + (16 * (pwm)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define F71882FG_REG_POINT_TEMP(pwm, point) (0xA6 + (point) + (16 * (pwm)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define F71882FG_REG_POINT_MAPPING(nr) (0xAF + 16 * (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define F71882FG_REG_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define F71882FG_MAX_INS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FAN_MIN_DETECT 366 /* Lowest detectable fanspeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static unsigned short force_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) module_param(force_id, ushort, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_PARM_DESC(force_id, "Override the detected device ID");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum chips { f71808e, f71808a, f71858fg, f71862fg, f71868a, f71869, f71869a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) f71882fg, f71889fg, f71889ed, f71889a, f8000, f81768d, f81865f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) f81866a};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char *const f71882fg_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "f71808e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "f71808a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "f71858fg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "f71862fg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "f71868a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "f71869", /* Both f71869f and f71869e, reg. compatible and same id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "f71869a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "f71882fg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "f71889fg", /* f81801u too, same id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "f71889ed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "f71889a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "f8000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "f81768d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "f81865f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "f81866a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char f71882fg_has_in[][F71882FG_MAX_INS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [f71808e] = { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [f71808a] = { 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [f71858fg] = { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [f71862fg] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [f71868a] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [f71869] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [f71869a] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [f71882fg] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [f71889fg] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [f71889ed] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [f71889a] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [f8000] = { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [f81768d] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [f81865f] = { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [f81866a] = { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char f71882fg_has_in1_alarm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [f71808e] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [f71808a] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [f71858fg] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [f71862fg] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [f71868a] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [f71869] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [f71869a] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [f71882fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [f71889fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [f71889ed] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [f71889a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [f8000] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [f81768d] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [f81865f] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [f81866a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char f71882fg_fan_has_beep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [f71808e] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [f71808a] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [f71858fg] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [f71862fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [f71868a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [f71869] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [f71869a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [f71882fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [f71889fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [f71889ed] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [f71889a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [f8000] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [f81768d] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [f81865f] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [f81866a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char f71882fg_nr_fans[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [f71808e] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [f71808a] = 2, /* +1 fan which is monitor + simple pwm only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [f71858fg] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [f71862fg] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [f71868a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [f71869] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [f71869a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [f71882fg] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [f71889fg] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [f71889ed] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [f71889a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [f8000] = 3, /* +1 fan which is monitor only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [f81768d] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [f81865f] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [f81866a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const char f71882fg_temp_has_beep[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [f71808e] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [f71808a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [f71858fg] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [f71862fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [f71868a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [f71869] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [f71869a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [f71882fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [f71889fg] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [f71889ed] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [f71889a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [f8000] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [f81768d] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [f81865f] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [f81866a] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const char f71882fg_nr_temps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [f71808e] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [f71808a] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [f71858fg] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [f71862fg] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [f71868a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [f71869] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [f71869a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [f71882fg] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [f71889fg] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [f71889ed] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [f71889a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [f8000] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [f81768d] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [f81865f] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [f81866a] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct platform_device *f71882fg_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Super-I/O Function prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline int superio_inb(int base, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline int superio_inw(int base, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline int superio_enter(int base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline void superio_select(int base, int ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline void superio_exit(int base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct f71882fg_sio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) enum chips type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct f71882fg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned short addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum chips type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int temp_start; /* temp numbering start (0 or 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) char valid; /* !=0 if following fields are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) char auto_point_temp_signed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long last_updated; /* In jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long last_limits; /* In jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Register Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 in[F71882FG_MAX_INS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 in1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 in_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 in_beep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u16 fan[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u16 fan_target[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u16 fan_full_speed[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 fan_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 fan_beep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Note: all models have max 3 temperature channels, but on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * they are addressed as 0-2 and on others as 1-3, so for coding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * convenience we reserve space for 4 channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u16 temp[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 temp_ovt[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 temp_high[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 temp_hyst[2]; /* 2 hysts stored per reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 temp_type[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 temp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 temp_beep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 temp_diode_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 temp_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 pwm[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 pwm_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 pwm_auto_point_hyst[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 pwm_auto_point_mapping[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 pwm_auto_point_pwm[4][5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) s8 pwm_auto_point_temp[4][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Sysfs in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static ssize_t show_in(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static ssize_t show_in_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static ssize_t store_in_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static ssize_t show_in_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static ssize_t store_in_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static ssize_t show_in_alarm(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Sysfs Fan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static ssize_t show_fan(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static ssize_t show_fan_full_speed(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static ssize_t store_fan_full_speed(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static ssize_t show_fan_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static ssize_t store_fan_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static ssize_t show_fan_alarm(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Sysfs Temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static ssize_t show_temp(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static ssize_t show_temp_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static ssize_t store_temp_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static ssize_t show_temp_max_hyst(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static ssize_t store_temp_max_hyst(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static ssize_t show_temp_crit(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static ssize_t store_temp_crit(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static ssize_t show_temp_crit_hyst(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static ssize_t show_temp_type(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static ssize_t show_temp_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static ssize_t store_temp_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static ssize_t show_temp_alarm(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static ssize_t show_temp_fault(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* PWM and Auto point control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static ssize_t show_pwm(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static ssize_t store_pwm(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static ssize_t show_simple_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static ssize_t store_simple_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static ssize_t show_pwm_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static ssize_t store_pwm_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static ssize_t show_pwm_interpolate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static ssize_t store_pwm_interpolate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static ssize_t show_pwm_auto_point_channel(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static ssize_t store_pwm_auto_point_channel(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static ssize_t show_pwm_auto_point_temp_hyst(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static ssize_t store_pwm_auto_point_temp_hyst(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static ssize_t show_pwm_auto_point_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static ssize_t store_pwm_auto_point_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static ssize_t show_pwm_auto_point_temp(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct device_attribute *devattr, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static ssize_t store_pwm_auto_point_temp(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct device_attribute *devattr, const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Sysfs misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static ssize_t name_show(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int f71882fg_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int f71882fg_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct platform_driver f71882fg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .probe = f71882fg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .remove = f71882fg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static DEVICE_ATTR_RO(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Temp attr for the f71858fg, the f71858fg is special as it has its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * temperature indexes start at 0 (the others start at 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct sensor_device_attribute_2 f71858fg_temp_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SENSOR_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SENSOR_ATTR_2(temp1_max, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) store_temp_max, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SENSOR_ATTR_2(temp1_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) store_temp_max_hyst, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SENSOR_ATTR_2(temp1_max_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SENSOR_ATTR_2(temp1_crit, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) store_temp_crit, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SENSOR_ATTR_2(temp1_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SENSOR_ATTR_2(temp1_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SENSOR_ATTR_2(temp1_fault, S_IRUGO, show_temp_fault, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SENSOR_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SENSOR_ATTR_2(temp2_max, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) store_temp_max, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SENSOR_ATTR_2(temp2_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) store_temp_max_hyst, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SENSOR_ATTR_2(temp2_max_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SENSOR_ATTR_2(temp2_crit, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) store_temp_crit, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SENSOR_ATTR_2(temp2_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SENSOR_ATTR_2(temp2_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) SENSOR_ATTR_2(temp2_fault, S_IRUGO, show_temp_fault, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SENSOR_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) SENSOR_ATTR_2(temp3_max, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) store_temp_max, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SENSOR_ATTR_2(temp3_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) store_temp_max_hyst, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SENSOR_ATTR_2(temp3_max_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) SENSOR_ATTR_2(temp3_crit, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) store_temp_crit, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) SENSOR_ATTR_2(temp3_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) SENSOR_ATTR_2(temp3_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SENSOR_ATTR_2(temp3_fault, S_IRUGO, show_temp_fault, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Temp attr for the standard models */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct sensor_device_attribute_2 fxxxx_temp_attr[3][9] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) SENSOR_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SENSOR_ATTR_2(temp1_max, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) store_temp_max, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SENSOR_ATTR_2(temp1_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) store_temp_max_hyst, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Should really be temp1_max_alarm, but older versions did not handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * the max and crit alarms separately and lm_sensors v2 depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * presence of temp#_alarm files. The same goes for temp2/3 _alarm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SENSOR_ATTR_2(temp1_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) SENSOR_ATTR_2(temp1_crit, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) store_temp_crit, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SENSOR_ATTR_2(temp1_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SENSOR_ATTR_2(temp1_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) SENSOR_ATTR_2(temp1_type, S_IRUGO, show_temp_type, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) SENSOR_ATTR_2(temp1_fault, S_IRUGO, show_temp_fault, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SENSOR_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SENSOR_ATTR_2(temp2_max, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) store_temp_max, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SENSOR_ATTR_2(temp2_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) store_temp_max_hyst, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Should be temp2_max_alarm, see temp1_alarm note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SENSOR_ATTR_2(temp2_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SENSOR_ATTR_2(temp2_crit, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) store_temp_crit, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SENSOR_ATTR_2(temp2_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SENSOR_ATTR_2(temp2_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SENSOR_ATTR_2(temp2_type, S_IRUGO, show_temp_type, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SENSOR_ATTR_2(temp2_fault, S_IRUGO, show_temp_fault, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SENSOR_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SENSOR_ATTR_2(temp3_max, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) store_temp_max, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SENSOR_ATTR_2(temp3_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) store_temp_max_hyst, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Should be temp3_max_alarm, see temp1_alarm note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SENSOR_ATTR_2(temp3_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SENSOR_ATTR_2(temp3_crit, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) store_temp_crit, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SENSOR_ATTR_2(temp3_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SENSOR_ATTR_2(temp3_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SENSOR_ATTR_2(temp3_type, S_IRUGO, show_temp_type, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SENSOR_ATTR_2(temp3_fault, S_IRUGO, show_temp_fault, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Temp attr for models which can beep on temp alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static struct sensor_device_attribute_2 fxxxx_temp_beep_attr[3][2] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SENSOR_ATTR_2(temp1_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) store_temp_beep, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SENSOR_ATTR_2(temp1_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) store_temp_beep, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SENSOR_ATTR_2(temp2_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) store_temp_beep, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SENSOR_ATTR_2(temp2_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) store_temp_beep, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SENSOR_ATTR_2(temp3_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) store_temp_beep, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SENSOR_ATTR_2(temp3_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) store_temp_beep, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct sensor_device_attribute_2 f81866_temp_beep_attr[3][2] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SENSOR_ATTR_2(temp1_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) store_temp_beep, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SENSOR_ATTR_2(temp1_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) store_temp_beep, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SENSOR_ATTR_2(temp2_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) store_temp_beep, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SENSOR_ATTR_2(temp2_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) store_temp_beep, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SENSOR_ATTR_2(temp3_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) store_temp_beep, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SENSOR_ATTR_2(temp3_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) store_temp_beep, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Temp attr for the f8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Note on the f8000 temp_ovt (crit) is used as max, and temp_high (max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * is used as hysteresis value to clear alarms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Also like the f71858fg its temperature indexes start at 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct sensor_device_attribute_2 f8000_temp_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) SENSOR_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SENSOR_ATTR_2(temp1_max, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) store_temp_crit, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SENSOR_ATTR_2(temp1_max_hyst, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) store_temp_max, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SENSOR_ATTR_2(temp1_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) SENSOR_ATTR_2(temp1_fault, S_IRUGO, show_temp_fault, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SENSOR_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SENSOR_ATTR_2(temp2_max, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) store_temp_crit, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SENSOR_ATTR_2(temp2_max_hyst, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) store_temp_max, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SENSOR_ATTR_2(temp2_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) SENSOR_ATTR_2(temp2_fault, S_IRUGO, show_temp_fault, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) SENSOR_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SENSOR_ATTR_2(temp3_max, S_IRUGO|S_IWUSR, show_temp_crit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) store_temp_crit, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SENSOR_ATTR_2(temp3_max_hyst, S_IRUGO|S_IWUSR, show_temp_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) store_temp_max, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SENSOR_ATTR_2(temp3_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SENSOR_ATTR_2(temp3_fault, S_IRUGO, show_temp_fault, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* in attr for all models */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct sensor_device_attribute_2 fxxxx_in_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) SENSOR_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) SENSOR_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SENSOR_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SENSOR_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SENSOR_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SENSOR_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SENSOR_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SENSOR_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) SENSOR_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) SENSOR_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SENSOR_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* For models with in1 alarm capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static struct sensor_device_attribute_2 fxxxx_in1_alarm_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SENSOR_ATTR_2(in1_max, S_IRUGO|S_IWUSR, show_in_max, store_in_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) SENSOR_ATTR_2(in1_beep, S_IRUGO|S_IWUSR, show_in_beep, store_in_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) SENSOR_ATTR_2(in1_alarm, S_IRUGO, show_in_alarm, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Fan / PWM attr common to all models */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct sensor_device_attribute_2 fxxxx_fan_attr[4][6] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SENSOR_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SENSOR_ATTR_2(fan1_full_speed, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) show_fan_full_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) store_fan_full_speed, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) SENSOR_ATTR_2(fan1_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) SENSOR_ATTR_2(pwm1, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SENSOR_ATTR_2(pwm1_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) store_pwm_enable, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SENSOR_ATTR_2(pwm1_interpolate, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) show_pwm_interpolate, store_pwm_interpolate, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SENSOR_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) SENSOR_ATTR_2(fan2_full_speed, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) show_fan_full_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) store_fan_full_speed, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SENSOR_ATTR_2(fan2_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SENSOR_ATTR_2(pwm2, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) SENSOR_ATTR_2(pwm2_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) store_pwm_enable, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SENSOR_ATTR_2(pwm2_interpolate, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) show_pwm_interpolate, store_pwm_interpolate, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SENSOR_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) SENSOR_ATTR_2(fan3_full_speed, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) show_fan_full_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) store_fan_full_speed, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) SENSOR_ATTR_2(fan3_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) SENSOR_ATTR_2(pwm3, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) SENSOR_ATTR_2(pwm3_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) store_pwm_enable, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) SENSOR_ATTR_2(pwm3_interpolate, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) show_pwm_interpolate, store_pwm_interpolate, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SENSOR_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SENSOR_ATTR_2(fan4_full_speed, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) show_fan_full_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) store_fan_full_speed, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) SENSOR_ATTR_2(fan4_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) SENSOR_ATTR_2(pwm4, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SENSOR_ATTR_2(pwm4_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) store_pwm_enable, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SENSOR_ATTR_2(pwm4_interpolate, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) show_pwm_interpolate, store_pwm_interpolate, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Attr for the third fan of the f71808a, which only has manual pwm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static struct sensor_device_attribute_2 f71808a_fan3_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) SENSOR_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SENSOR_ATTR_2(fan3_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) SENSOR_ATTR_2(pwm3, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) show_simple_pwm, store_simple_pwm, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Attr for models which can beep on Fan alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct sensor_device_attribute_2 fxxxx_fan_beep_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SENSOR_ATTR_2(fan1_beep, S_IRUGO|S_IWUSR, show_fan_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) store_fan_beep, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SENSOR_ATTR_2(fan2_beep, S_IRUGO|S_IWUSR, show_fan_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) store_fan_beep, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SENSOR_ATTR_2(fan3_beep, S_IRUGO|S_IWUSR, show_fan_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) store_fan_beep, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SENSOR_ATTR_2(fan4_beep, S_IRUGO|S_IWUSR, show_fan_beep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) store_fan_beep, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * PWM attr for the f71862fg, fewer pwms and fewer zones per pwm than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * standard models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static struct sensor_device_attribute_2 f71862fg_auto_pwm_attr[3][7] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) SENSOR_ATTR_2(pwm1_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) store_pwm_auto_point_channel, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SENSOR_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SENSOR_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SENSOR_ATTR_2(pwm1_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SENSOR_ATTR_2(pwm1_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) SENSOR_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) SENSOR_ATTR_2(pwm1_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) show_pwm_auto_point_temp_hyst, NULL, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) SENSOR_ATTR_2(pwm2_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) store_pwm_auto_point_channel, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) SENSOR_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) SENSOR_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) SENSOR_ATTR_2(pwm2_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SENSOR_ATTR_2(pwm2_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) SENSOR_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) SENSOR_ATTR_2(pwm2_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) show_pwm_auto_point_temp_hyst, NULL, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SENSOR_ATTR_2(pwm3_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) store_pwm_auto_point_channel, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) SENSOR_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SENSOR_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) SENSOR_ATTR_2(pwm3_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) SENSOR_ATTR_2(pwm3_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) SENSOR_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) SENSOR_ATTR_2(pwm3_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) show_pwm_auto_point_temp_hyst, NULL, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * PWM attr for the f71808e/f71869, almost identical to the f71862fg, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * pwm setting when the temperature is above the pwmX_auto_point1_temp can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * programmed instead of being hardcoded to 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static struct sensor_device_attribute_2 f71869_auto_pwm_attr[3][8] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) SENSOR_ATTR_2(pwm1_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) store_pwm_auto_point_channel, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) SENSOR_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SENSOR_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) SENSOR_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) SENSOR_ATTR_2(pwm1_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) SENSOR_ATTR_2(pwm1_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) SENSOR_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) SENSOR_ATTR_2(pwm1_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) show_pwm_auto_point_temp_hyst, NULL, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) SENSOR_ATTR_2(pwm2_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) store_pwm_auto_point_channel, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) SENSOR_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) SENSOR_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SENSOR_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) SENSOR_ATTR_2(pwm2_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) SENSOR_ATTR_2(pwm2_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) SENSOR_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) SENSOR_ATTR_2(pwm2_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) show_pwm_auto_point_temp_hyst, NULL, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) SENSOR_ATTR_2(pwm3_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) store_pwm_auto_point_channel, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) SENSOR_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) SENSOR_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SENSOR_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) SENSOR_ATTR_2(pwm3_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SENSOR_ATTR_2(pwm3_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SENSOR_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) SENSOR_ATTR_2(pwm3_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) show_pwm_auto_point_temp_hyst, NULL, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* PWM attr for the standard models */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static struct sensor_device_attribute_2 fxxxx_auto_pwm_attr[4][14] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) SENSOR_ATTR_2(pwm1_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) store_pwm_auto_point_channel, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) SENSOR_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) SENSOR_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) SENSOR_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SENSOR_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) SENSOR_ATTR_2(pwm1_auto_point5_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) SENSOR_ATTR_2(pwm1_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SENSOR_ATTR_2(pwm1_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) SENSOR_ATTR_2(pwm1_auto_point3_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SENSOR_ATTR_2(pwm1_auto_point4_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SENSOR_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) SENSOR_ATTR_2(pwm1_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) show_pwm_auto_point_temp_hyst, NULL, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SENSOR_ATTR_2(pwm1_auto_point3_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) show_pwm_auto_point_temp_hyst, NULL, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) SENSOR_ATTR_2(pwm1_auto_point4_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) show_pwm_auto_point_temp_hyst, NULL, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) SENSOR_ATTR_2(pwm2_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) store_pwm_auto_point_channel, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) SENSOR_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SENSOR_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SENSOR_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SENSOR_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) SENSOR_ATTR_2(pwm2_auto_point5_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) SENSOR_ATTR_2(pwm2_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) SENSOR_ATTR_2(pwm2_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SENSOR_ATTR_2(pwm2_auto_point3_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) SENSOR_ATTR_2(pwm2_auto_point4_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) SENSOR_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SENSOR_ATTR_2(pwm2_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) show_pwm_auto_point_temp_hyst, NULL, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) SENSOR_ATTR_2(pwm2_auto_point3_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) show_pwm_auto_point_temp_hyst, NULL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) SENSOR_ATTR_2(pwm2_auto_point4_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) show_pwm_auto_point_temp_hyst, NULL, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SENSOR_ATTR_2(pwm3_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) store_pwm_auto_point_channel, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SENSOR_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) SENSOR_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) SENSOR_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SENSOR_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) SENSOR_ATTR_2(pwm3_auto_point5_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) SENSOR_ATTR_2(pwm3_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) SENSOR_ATTR_2(pwm3_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SENSOR_ATTR_2(pwm3_auto_point3_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) SENSOR_ATTR_2(pwm3_auto_point4_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SENSOR_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) SENSOR_ATTR_2(pwm3_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) show_pwm_auto_point_temp_hyst, NULL, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) SENSOR_ATTR_2(pwm3_auto_point3_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) show_pwm_auto_point_temp_hyst, NULL, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) SENSOR_ATTR_2(pwm3_auto_point4_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) show_pwm_auto_point_temp_hyst, NULL, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) SENSOR_ATTR_2(pwm4_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) store_pwm_auto_point_channel, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SENSOR_ATTR_2(pwm4_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SENSOR_ATTR_2(pwm4_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SENSOR_ATTR_2(pwm4_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SENSOR_ATTR_2(pwm4_auto_point4_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) SENSOR_ATTR_2(pwm4_auto_point5_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) SENSOR_ATTR_2(pwm4_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) SENSOR_ATTR_2(pwm4_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SENSOR_ATTR_2(pwm4_auto_point3_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) SENSOR_ATTR_2(pwm4_auto_point4_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) SENSOR_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) SENSOR_ATTR_2(pwm4_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) show_pwm_auto_point_temp_hyst, NULL, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) SENSOR_ATTR_2(pwm4_auto_point3_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) show_pwm_auto_point_temp_hyst, NULL, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) SENSOR_ATTR_2(pwm4_auto_point4_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) show_pwm_auto_point_temp_hyst, NULL, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* Fan attr specific to the f8000 (4th fan input can only measure speed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static struct sensor_device_attribute_2 f8000_fan_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) SENSOR_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * PWM attr for the f8000, zones mapped to temp instead of to pwm!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * Also the register block at offset A0 maps to TEMP1 (so our temp2, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * F8000 starts counting temps at 0), B0 maps the TEMP2 and C0 maps to TEMP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static struct sensor_device_attribute_2 f8000_auto_pwm_attr[3][14] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) SENSOR_ATTR_2(pwm1_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) store_pwm_auto_point_channel, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) SENSOR_ATTR_2(temp1_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) SENSOR_ATTR_2(temp1_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) SENSOR_ATTR_2(temp1_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) SENSOR_ATTR_2(temp1_auto_point4_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SENSOR_ATTR_2(temp1_auto_point5_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) SENSOR_ATTR_2(temp1_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) SENSOR_ATTR_2(temp1_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) SENSOR_ATTR_2(temp1_auto_point3_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) SENSOR_ATTR_2(temp1_auto_point4_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) SENSOR_ATTR_2(temp1_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) SENSOR_ATTR_2(temp1_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) show_pwm_auto_point_temp_hyst, NULL, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) SENSOR_ATTR_2(temp1_auto_point3_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) show_pwm_auto_point_temp_hyst, NULL, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) SENSOR_ATTR_2(temp1_auto_point4_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) show_pwm_auto_point_temp_hyst, NULL, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) SENSOR_ATTR_2(pwm2_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) store_pwm_auto_point_channel, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) SENSOR_ATTR_2(temp2_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) SENSOR_ATTR_2(temp2_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) SENSOR_ATTR_2(temp2_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) SENSOR_ATTR_2(temp2_auto_point4_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) SENSOR_ATTR_2(temp2_auto_point5_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) SENSOR_ATTR_2(temp2_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) SENSOR_ATTR_2(temp2_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) SENSOR_ATTR_2(temp2_auto_point3_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) SENSOR_ATTR_2(temp2_auto_point4_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) SENSOR_ATTR_2(temp2_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) SENSOR_ATTR_2(temp2_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) show_pwm_auto_point_temp_hyst, NULL, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) SENSOR_ATTR_2(temp2_auto_point3_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) show_pwm_auto_point_temp_hyst, NULL, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) SENSOR_ATTR_2(temp2_auto_point4_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) show_pwm_auto_point_temp_hyst, NULL, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) SENSOR_ATTR_2(pwm3_auto_channels_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) show_pwm_auto_point_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) store_pwm_auto_point_channel, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) SENSOR_ATTR_2(temp3_auto_point1_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) SENSOR_ATTR_2(temp3_auto_point2_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SENSOR_ATTR_2(temp3_auto_point3_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) SENSOR_ATTR_2(temp3_auto_point4_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) SENSOR_ATTR_2(temp3_auto_point5_pwm, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) SENSOR_ATTR_2(temp3_auto_point1_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) SENSOR_ATTR_2(temp3_auto_point2_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) SENSOR_ATTR_2(temp3_auto_point3_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) SENSOR_ATTR_2(temp3_auto_point4_temp, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) show_pwm_auto_point_temp, store_pwm_auto_point_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) SENSOR_ATTR_2(temp3_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) show_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) store_pwm_auto_point_temp_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SENSOR_ATTR_2(temp3_auto_point2_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) show_pwm_auto_point_temp_hyst, NULL, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) SENSOR_ATTR_2(temp3_auto_point3_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) show_pwm_auto_point_temp_hyst, NULL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) SENSOR_ATTR_2(temp3_auto_point4_temp_hyst, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) show_pwm_auto_point_temp_hyst, NULL, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Super I/O functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static inline int superio_inb(int base, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) outb(reg, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return inb(base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int superio_inw(int base, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) val = superio_inb(base, reg) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) val |= superio_inb(base, reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static inline int superio_enter(int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Don't step on other drivers' I/O space by accident */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (!request_muxed_region(base, 2, DRVNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) pr_err("I/O address 0x%04x already in use\n", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* according to the datasheet the key must be send twice! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) outb(SIO_UNLOCK_KEY, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) outb(SIO_UNLOCK_KEY, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static inline void superio_select(int base, int ld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) outb(SIO_REG_LDSEL, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) outb(ld, base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static inline void superio_exit(int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) outb(SIO_LOCK_KEY, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) release_region(base, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static inline int fan_from_reg(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return reg ? (1500000 / reg) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static inline u16 fan_to_reg(int fan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return fan ? (1500000 / fan) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static u8 f71882fg_read8(struct f71882fg_data *data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) outb(reg, data->addr + ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) val = inb(data->addr + DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static u16 f71882fg_read16(struct f71882fg_data *data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) val = f71882fg_read8(data, reg) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) val |= f71882fg_read8(data, reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static void f71882fg_write8(struct f71882fg_data *data, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) outb(reg, data->addr + ADDR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) outb(val, data->addr + DATA_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static void f71882fg_write16(struct f71882fg_data *data, u8 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) f71882fg_write8(data, reg, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) f71882fg_write8(data, reg + 1, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static u16 f71882fg_read_temp(struct f71882fg_data *data, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (data->type == f71858fg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return f71882fg_read16(data, F71882FG_REG_TEMP(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return f71882fg_read8(data, F71882FG_REG_TEMP(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static struct f71882fg_data *f71882fg_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) int nr_fans = f71882fg_nr_fans[data->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) int nr_temps = f71882fg_nr_temps[data->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) int nr, reg, point;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Update once every 60 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (time_after(jiffies, data->last_limits + 60 * HZ) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (f71882fg_has_in1_alarm[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (data->type == f81866a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) data->in1_max =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) F81866_REG_IN1_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) data->in_beep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) F81866_REG_IN_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) data->in1_max =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) F71882FG_REG_IN1_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) data->in_beep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) F71882FG_REG_IN_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* Get High & boundary temps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) for (nr = data->temp_start; nr < nr_temps + data->temp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) nr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) data->temp_ovt[nr] = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) F71882FG_REG_TEMP_OVT(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) data->temp_high[nr] = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) F71882FG_REG_TEMP_HIGH(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (data->type != f8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) data->temp_hyst[0] = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) F71882FG_REG_TEMP_HYST(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) data->temp_hyst[1] = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) F71882FG_REG_TEMP_HYST(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* All but the f71858fg / f8000 have this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if ((data->type != f71858fg) && (data->type != f8000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) reg = f71882fg_read8(data, F71882FG_REG_TEMP_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) data->temp_type[1] = (reg & 0x02) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) data->temp_type[2] = (reg & 0x04) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) data->temp_type[3] = (reg & 0x08) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (f71882fg_fan_has_beep[data->type])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) data->fan_beep = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) F71882FG_REG_FAN_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (f71882fg_temp_has_beep[data->type])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) data->temp_beep = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) F71882FG_REG_TEMP_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) data->pwm_enable = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) F71882FG_REG_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) data->pwm_auto_point_hyst[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) f71882fg_read8(data, F71882FG_REG_FAN_HYST(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) data->pwm_auto_point_hyst[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) f71882fg_read8(data, F71882FG_REG_FAN_HYST(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) for (nr = 0; nr < nr_fans; nr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) data->pwm_auto_point_mapping[nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) F71882FG_REG_POINT_MAPPING(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) for (point = 0; point < 5; point++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) data->pwm_auto_point_pwm[nr][point] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) F71882FG_REG_POINT_PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) (nr, point));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) for (point = 0; point < 4; point++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) data->pwm_auto_point_temp[nr][point] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) F71882FG_REG_POINT_TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) (nr, point));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case f71808e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) case f71869:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) data->pwm_auto_point_pwm[nr][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) F71882FG_REG_POINT_PWM(nr, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) case f71862fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) data->pwm_auto_point_pwm[nr][1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) F71882FG_REG_POINT_PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) (nr, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) data->pwm_auto_point_pwm[nr][4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) F71882FG_REG_POINT_PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) (nr, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) data->pwm_auto_point_temp[nr][0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) F71882FG_REG_POINT_TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) (nr, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) data->pwm_auto_point_temp[nr][3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) F71882FG_REG_POINT_TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) (nr, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) data->last_limits = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Update every second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) data->temp_status = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) F71882FG_REG_TEMP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) data->temp_diode_open = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) F71882FG_REG_TEMP_DIODE_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) for (nr = data->temp_start; nr < nr_temps + data->temp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) nr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) data->temp[nr] = f71882fg_read_temp(data, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) data->fan_status = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) F71882FG_REG_FAN_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) for (nr = 0; nr < nr_fans; nr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) data->fan[nr] = f71882fg_read16(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) F71882FG_REG_FAN(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) data->fan_target[nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) f71882fg_read16(data, F71882FG_REG_FAN_TARGET(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) data->fan_full_speed[nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) f71882fg_read16(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) F71882FG_REG_FAN_FULL_SPEED(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) data->pwm[nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) f71882fg_read8(data, F71882FG_REG_PWM(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Some models have 1 more fan with limited capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (data->type == f71808a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) data->fan[2] = f71882fg_read16(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) F71882FG_REG_FAN(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) data->pwm[2] = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) F71882FG_REG_PWM(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (data->type == f8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) data->fan[3] = f71882fg_read16(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) F71882FG_REG_FAN(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (f71882fg_has_in1_alarm[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (data->type == f81866a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) data->in_status = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) F81866_REG_IN_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) data->in_status = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) F71882FG_REG_IN_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) for (nr = 0; nr < F71882FG_MAX_INS; nr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (f71882fg_has_in[data->type][nr])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) data->in[nr] = f71882fg_read8(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) F71882FG_REG_IN(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* Sysfs Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static ssize_t show_fan(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) int speed = fan_from_reg(data->fan[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (speed == FAN_MIN_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return sprintf(buf, "%d\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static ssize_t show_fan_full_speed(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct device_attribute *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) int speed = fan_from_reg(data->fan_full_speed[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return sprintf(buf, "%d\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static ssize_t store_fan_full_speed(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) val = clamp_val(val, 23, 1500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) val = fan_to_reg(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) f71882fg_write16(data, F71882FG_REG_FAN_FULL_SPEED(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) data->fan_full_speed[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static ssize_t show_fan_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (data->fan_beep & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return sprintf(buf, "1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static ssize_t store_fan_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) data->fan_beep = f71882fg_read8(data, F71882FG_REG_FAN_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) data->fan_beep |= 1 << nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) data->fan_beep &= ~(1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) f71882fg_write8(data, F71882FG_REG_FAN_BEEP, data->fan_beep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static ssize_t show_fan_alarm(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (data->fan_status & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return sprintf(buf, "1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static ssize_t show_in(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return sprintf(buf, "%d\n", data->in[nr] * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static ssize_t show_in_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return sprintf(buf, "%d\n", data->in1_max * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static ssize_t store_in_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) val /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (data->type == f81866a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) f71882fg_write8(data, F81866_REG_IN1_HIGH, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) f71882fg_write8(data, F71882FG_REG_IN1_HIGH, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) data->in1_max = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static ssize_t show_in_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (data->in_beep & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return sprintf(buf, "1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static ssize_t store_in_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (data->type == f81866a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) data->in_beep = f71882fg_read8(data, F81866_REG_IN_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) data->in_beep = f71882fg_read8(data, F71882FG_REG_IN_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) data->in_beep |= 1 << nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) data->in_beep &= ~(1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (data->type == f81866a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) f71882fg_write8(data, F81866_REG_IN_BEEP, data->in_beep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) f71882fg_write8(data, F71882FG_REG_IN_BEEP, data->in_beep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static ssize_t show_in_alarm(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (data->in_status & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return sprintf(buf, "1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static ssize_t show_temp(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) int sign, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (data->type == f71858fg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* TEMP_TABLE_SEL 1 or 3 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (data->temp_config & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) sign = data->temp[nr] & 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) temp = (data->temp[nr] >> 5) & 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) sign = data->temp[nr] & 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) temp = (data->temp[nr] >> 5) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) temp *= 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (sign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) temp -= 128000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) temp = data->temp[nr] * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return sprintf(buf, "%d\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static ssize_t show_temp_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return sprintf(buf, "%d\n", data->temp_high[nr] * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static ssize_t store_temp_max(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) f71882fg_write8(data, F71882FG_REG_TEMP_HIGH(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) data->temp_high[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static ssize_t show_temp_max_hyst(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) int temp_max_hyst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (nr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) temp_max_hyst = data->temp_hyst[nr / 2] >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) temp_max_hyst = data->temp_hyst[nr / 2] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) temp_max_hyst = (data->temp_high[nr] - temp_max_hyst) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return sprintf(buf, "%d\n", temp_max_hyst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static ssize_t store_temp_max_hyst(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ssize_t ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* convert abs to relative and check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) data->temp_high[nr] = f71882fg_read8(data, F71882FG_REG_TEMP_HIGH(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) val = clamp_val(val, data->temp_high[nr] - 15, data->temp_high[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) val = data->temp_high[nr] - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* convert value to register contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) reg = f71882fg_read8(data, F71882FG_REG_TEMP_HYST(nr / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (nr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) reg = (reg & 0x0f) | (val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) reg = (reg & 0xf0) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) f71882fg_write8(data, F71882FG_REG_TEMP_HYST(nr / 2), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) data->temp_hyst[nr / 2] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static ssize_t show_temp_crit(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return sprintf(buf, "%d\n", data->temp_ovt[nr] * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static ssize_t store_temp_crit(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) f71882fg_write8(data, F71882FG_REG_TEMP_OVT(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) data->temp_ovt[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static ssize_t show_temp_crit_hyst(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) int temp_crit_hyst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (nr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) temp_crit_hyst = data->temp_hyst[nr / 2] >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) temp_crit_hyst = data->temp_hyst[nr / 2] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) temp_crit_hyst = (data->temp_ovt[nr] - temp_crit_hyst) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return sprintf(buf, "%d\n", temp_crit_hyst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static ssize_t show_temp_type(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) return sprintf(buf, "%d\n", data->temp_type[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static ssize_t show_temp_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (data->temp_beep & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return sprintf(buf, "1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static ssize_t store_temp_beep(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) data->temp_beep = f71882fg_read8(data, F71882FG_REG_TEMP_BEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) data->temp_beep |= 1 << nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) data->temp_beep &= ~(1 << nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) f71882fg_write8(data, F71882FG_REG_TEMP_BEEP, data->temp_beep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static ssize_t show_temp_alarm(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (data->temp_status & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return sprintf(buf, "1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static ssize_t show_temp_fault(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (data->temp_diode_open & (1 << nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return sprintf(buf, "1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static ssize_t show_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct device_attribute *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) int val, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (data->pwm_enable & (1 << (2 * nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) val = data->pwm[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* RPM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) val = 255 * fan_from_reg(data->fan_target[nr])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) / fan_from_reg(data->fan_full_speed[nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static ssize_t store_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct device_attribute *devattr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) data->pwm_enable = f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if ((data->type == f8000 && ((data->pwm_enable >> 2 * nr) & 3) != 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) (data->type != f8000 && !((data->pwm_enable >> 2 * nr) & 2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) count = -EROFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (data->pwm_enable & (1 << (2 * nr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) f71882fg_write8(data, F71882FG_REG_PWM(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) data->pwm[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* RPM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) int target, full_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) full_speed = f71882fg_read16(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) F71882FG_REG_FAN_FULL_SPEED(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) target = fan_to_reg(val * fan_from_reg(full_speed) / 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) f71882fg_write16(data, F71882FG_REG_FAN_TARGET(nr), target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) data->fan_target[nr] = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) data->fan_full_speed[nr] = full_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static ssize_t show_simple_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) struct device_attribute *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) int val, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) val = data->pwm[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static ssize_t store_simple_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) f71882fg_write8(data, F71882FG_REG_PWM(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) data->pwm[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static ssize_t show_pwm_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) struct device_attribute *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) switch ((data->pwm_enable >> 2 * nr) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) result = 2; /* Normal auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) result = 1; /* Manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (data->type == f8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) result = 3; /* Thermostat mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) result = 1; /* Manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return sprintf(buf, "%d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static ssize_t store_pwm_enable(struct device *dev, struct device_attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) *devattr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* Special case for F8000 pwm channel 3 which only does auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (data->type == f8000 && nr == 2 && val != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) data->pwm_enable = f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /* Special case for F8000 auto PWM mode / Thermostat mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (data->type == f8000 && ((data->pwm_enable >> 2 * nr) & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) data->pwm_enable &= ~(2 << (2 * nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) break; /* Normal auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) data->pwm_enable |= 2 << (2 * nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) break; /* Thermostat mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* The f71858fg does not support manual RPM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (data->type == f71858fg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ((data->pwm_enable >> (2 * nr)) & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) data->pwm_enable |= 2 << (2 * nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) break; /* Manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) data->pwm_enable &= ~(2 << (2 * nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) break; /* Normal auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) f71882fg_write8(data, F71882FG_REG_PWM_ENABLE, data->pwm_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static ssize_t show_pwm_auto_point_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) int pwm = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) int point = to_sensor_dev_attr_2(devattr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (data->pwm_enable & (1 << (2 * pwm))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) /* PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) result = data->pwm_auto_point_pwm[pwm][point];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* RPM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) result = 32 * 255 / (32 + data->pwm_auto_point_pwm[pwm][point]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return sprintf(buf, "%d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static ssize_t store_pwm_auto_point_pwm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) int err, pwm = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) int point = to_sensor_dev_attr_2(devattr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) val = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) data->pwm_enable = f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (data->pwm_enable & (1 << (2 * pwm))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /* PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /* RPM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (val < 29) /* Prevent negative numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) val = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) val = (255 - val) * 32 / val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) f71882fg_write8(data, F71882FG_REG_POINT_PWM(pwm, point), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) data->pwm_auto_point_pwm[pwm][point] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static ssize_t show_pwm_auto_point_temp_hyst(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) int point = to_sensor_dev_attr_2(devattr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (nr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) result = data->pwm_auto_point_hyst[nr / 2] >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) result = data->pwm_auto_point_hyst[nr / 2] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) result = 1000 * (data->pwm_auto_point_temp[nr][point] - result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) return sprintf(buf, "%d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static ssize_t store_pwm_auto_point_temp_hyst(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int point = to_sensor_dev_attr_2(devattr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) data->pwm_auto_point_temp[nr][point] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) f71882fg_read8(data, F71882FG_REG_POINT_TEMP(nr, point));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) val = clamp_val(val, data->pwm_auto_point_temp[nr][point] - 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) data->pwm_auto_point_temp[nr][point]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) val = data->pwm_auto_point_temp[nr][point] - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) reg = f71882fg_read8(data, F71882FG_REG_FAN_HYST(nr / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (nr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) reg = (reg & 0x0f) | (val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) reg = (reg & 0xf0) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) f71882fg_write8(data, F71882FG_REG_FAN_HYST(nr / 2), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) data->pwm_auto_point_hyst[nr / 2] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static ssize_t show_pwm_interpolate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) struct device_attribute *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) result = (data->pwm_auto_point_mapping[nr] >> 4) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return sprintf(buf, "%d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static ssize_t store_pwm_interpolate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) data->pwm_auto_point_mapping[nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) f71882fg_read8(data, F71882FG_REG_POINT_MAPPING(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) val = data->pwm_auto_point_mapping[nr] | (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) val = data->pwm_auto_point_mapping[nr] & (~(1 << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) f71882fg_write8(data, F71882FG_REG_POINT_MAPPING(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) data->pwm_auto_point_mapping[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) static ssize_t show_pwm_auto_point_channel(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) int nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) result = 1 << ((data->pwm_auto_point_mapping[nr] & 3) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) data->temp_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) return sprintf(buf, "%d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static ssize_t store_pwm_auto_point_channel(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) int err, nr = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) val += data->temp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) data->pwm_auto_point_mapping[nr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) f71882fg_read8(data, F71882FG_REG_POINT_MAPPING(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) val = (data->pwm_auto_point_mapping[nr] & 0xfc) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) f71882fg_write8(data, F71882FG_REG_POINT_MAPPING(nr), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) data->pwm_auto_point_mapping[nr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static ssize_t show_pwm_auto_point_temp(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) struct f71882fg_data *data = f71882fg_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) int pwm = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) int point = to_sensor_dev_attr_2(devattr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) result = data->pwm_auto_point_temp[pwm][point];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return sprintf(buf, "%d\n", 1000 * result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static ssize_t store_pwm_auto_point_temp(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) int err, pwm = to_sensor_dev_attr_2(devattr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) int point = to_sensor_dev_attr_2(devattr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (data->auto_point_temp_signed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) val = clamp_val(val, -128, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) val = clamp_val(val, 0, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) f71882fg_write8(data, F71882FG_REG_POINT_TEMP(pwm, point), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) data->pwm_auto_point_temp[pwm][point] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static ssize_t name_show(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) struct f71882fg_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) return sprintf(buf, "%s\n", f71882fg_names[data->type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static int f71882fg_create_sysfs_files(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct sensor_device_attribute_2 *attr, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) err = device_create_file(&pdev->dev, &attr[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) static void f71882fg_remove_sysfs_files(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) struct sensor_device_attribute_2 *attr, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) device_remove_file(&pdev->dev, &attr[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) static int f71882fg_create_fan_sysfs_files(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct platform_device *pdev, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct f71882fg_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /* Sanity check the pwm setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) case f71858fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (((data->pwm_enable >> (idx * 2)) & 3) == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) case f71862fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (((data->pwm_enable >> (idx * 2)) & 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) case f8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (idx == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) err = data->pwm_enable & 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) "Invalid (reserved) pwm settings: 0x%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) "skipping fan %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) (data->pwm_enable >> (idx * 2)) & 3, idx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return 0; /* This is a non fatal condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) err = f71882fg_create_sysfs_files(pdev, &fxxxx_fan_attr[idx][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) ARRAY_SIZE(fxxxx_fan_attr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (f71882fg_fan_has_beep[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) &fxxxx_fan_beep_attr[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) dev_info(&pdev->dev, "Fan: %d is in %s mode\n", idx + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) (data->pwm_enable & (1 << (2 * idx))) ? "duty-cycle" : "RPM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* Check for unsupported auto pwm settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) case f71808e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) case f71808a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) case f71869:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) case f71869a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) case f71889fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) case f71889ed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) case f71889a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) data->pwm_auto_point_mapping[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) f71882fg_read8(data, F71882FG_REG_POINT_MAPPING(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if ((data->pwm_auto_point_mapping[idx] & 0x80) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) (data->pwm_auto_point_mapping[idx] & 3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) "Auto pwm controlled by raw digital "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) "data, disabling pwm auto_point "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) "sysfs attributes for fan %d\n", idx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return 0; /* This is a non fatal condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) case f71862fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) &f71862fg_auto_pwm_attr[idx][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) ARRAY_SIZE(f71862fg_auto_pwm_attr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) case f71808e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) case f71869:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) &f71869_auto_pwm_attr[idx][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) ARRAY_SIZE(f71869_auto_pwm_attr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) case f8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) &f8000_auto_pwm_attr[idx][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ARRAY_SIZE(f8000_auto_pwm_attr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) &fxxxx_auto_pwm_attr[idx][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) ARRAY_SIZE(fxxxx_auto_pwm_attr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) static int f71882fg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) struct f71882fg_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) struct f71882fg_sio_data *sio_data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) int nr_fans = f71882fg_nr_fans[sio_data->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) int nr_temps = f71882fg_nr_temps[sio_data->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) u8 start_reg, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) data = devm_kzalloc(&pdev->dev, sizeof(struct f71882fg_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) data->type = sio_data->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) data->temp_start =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) (data->type == f71858fg || data->type == f8000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) data->type == f81866a) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) start_reg = f71882fg_read8(data, F71882FG_REG_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (start_reg & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) dev_warn(&pdev->dev, "Hardware monitor is powered down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) if (!(start_reg & 0x03)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) dev_warn(&pdev->dev, "Hardware monitoring not activated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /* Register sysfs interface files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) err = device_create_file(&pdev->dev, &dev_attr_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) if (start_reg & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) case f71858fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) data->temp_config =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) f71882fg_read8(data, F71882FG_REG_TEMP_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if (data->temp_config & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) * The f71858fg temperature alarms behave as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) * the f8000 alarms in this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) f8000_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ARRAY_SIZE(f8000_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) f71858fg_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) ARRAY_SIZE(f71858fg_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) case f8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) f8000_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ARRAY_SIZE(f8000_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) case f81866a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) f71858fg_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ARRAY_SIZE(f71858fg_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) &fxxxx_temp_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) ARRAY_SIZE(fxxxx_temp_attr[0]) * nr_temps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) if (f71882fg_temp_has_beep[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (data->type == f81866a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) size = ARRAY_SIZE(f81866_temp_beep_attr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) &f81866_temp_beep_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) size * nr_temps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) size = ARRAY_SIZE(fxxxx_temp_beep_attr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) &fxxxx_temp_beep_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) size * nr_temps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) for (i = 0; i < F71882FG_MAX_INS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (f71882fg_has_in[data->type][i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) err = device_create_file(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) &fxxxx_in_attr[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (f71882fg_has_in1_alarm[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) fxxxx_in1_alarm_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ARRAY_SIZE(fxxxx_in1_alarm_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (start_reg & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) case f71808e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) case f71808a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) case f71869:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) case f71869a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /* These always have signed auto point temps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) data->auto_point_temp_signed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) fallthrough; /* to select correct fan/pwm reg bank! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) case f71889fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) case f71889ed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) case f71889a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) reg = f71882fg_read8(data, F71882FG_REG_FAN_FAULT_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) if (reg & F71882FG_FAN_NEG_TEMP_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) data->auto_point_temp_signed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) /* Ensure banked pwm registers point to right bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) reg &= ~F71882FG_FAN_PROG_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) f71882fg_write8(data, F71882FG_REG_FAN_FAULT_T, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) data->pwm_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) for (i = 0; i < nr_fans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) err = f71882fg_create_fan_sysfs_files(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) /* Some types have 1 extra fan with limited functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) case f71808a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) f71808a_fan3_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ARRAY_SIZE(f71808a_fan3_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) case f8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) err = f71882fg_create_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) f8000_fan_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ARRAY_SIZE(f8000_fan_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) data->hwmon_dev = hwmon_device_register(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) if (IS_ERR(data->hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) err = PTR_ERR(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) data->hwmon_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) goto exit_unregister_sysfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) exit_unregister_sysfs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) f71882fg_remove(pdev); /* Will unregister the sysfs files for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) return err; /* f71882fg_remove() also frees our data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) static int f71882fg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct f71882fg_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) int nr_fans = f71882fg_nr_fans[data->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) int nr_temps = f71882fg_nr_temps[data->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) u8 start_reg = f71882fg_read8(data, F71882FG_REG_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) if (data->hwmon_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) hwmon_device_unregister(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) device_remove_file(&pdev->dev, &dev_attr_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (start_reg & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) case f71858fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) if (data->temp_config & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) f8000_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) ARRAY_SIZE(f8000_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) f71858fg_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) ARRAY_SIZE(f71858fg_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) case f8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) f8000_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) ARRAY_SIZE(f8000_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) case f81866a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) f71858fg_temp_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ARRAY_SIZE(f71858fg_temp_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) &fxxxx_temp_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) ARRAY_SIZE(fxxxx_temp_attr[0]) * nr_temps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) if (f71882fg_temp_has_beep[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if (data->type == f81866a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) &f81866_temp_beep_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) ARRAY_SIZE(f81866_temp_beep_attr[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * nr_temps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) &fxxxx_temp_beep_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) ARRAY_SIZE(fxxxx_temp_beep_attr[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) * nr_temps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) for (i = 0; i < F71882FG_MAX_INS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (f71882fg_has_in[data->type][i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) device_remove_file(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) &fxxxx_in_attr[i].dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) if (f71882fg_has_in1_alarm[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) fxxxx_in1_alarm_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ARRAY_SIZE(fxxxx_in1_alarm_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) if (start_reg & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) f71882fg_remove_sysfs_files(pdev, &fxxxx_fan_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ARRAY_SIZE(fxxxx_fan_attr[0]) * nr_fans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) if (f71882fg_fan_has_beep[data->type]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) fxxxx_fan_beep_attr, nr_fans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) case f71808a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) &fxxxx_auto_pwm_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) ARRAY_SIZE(fxxxx_auto_pwm_attr[0]) * nr_fans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) f71808a_fan3_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) ARRAY_SIZE(f71808a_fan3_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) case f71862fg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) &f71862fg_auto_pwm_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) ARRAY_SIZE(f71862fg_auto_pwm_attr[0]) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) nr_fans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) case f71808e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) case f71869:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) &f71869_auto_pwm_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) ARRAY_SIZE(f71869_auto_pwm_attr[0]) * nr_fans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) case f8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) f8000_fan_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) ARRAY_SIZE(f8000_fan_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) &f8000_auto_pwm_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) ARRAY_SIZE(f8000_auto_pwm_attr[0]) * nr_fans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) f71882fg_remove_sysfs_files(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) &fxxxx_auto_pwm_attr[0][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) ARRAY_SIZE(fxxxx_auto_pwm_attr[0]) * nr_fans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) static int __init f71882fg_find(int sioaddr, struct f71882fg_sio_data *sio_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) u16 devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) unsigned short address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) int err = superio_enter(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) devid = superio_inw(sioaddr, SIO_REG_MANID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (devid != SIO_FINTEK_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) pr_debug("Not a Fintek device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) switch (devid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case SIO_F71808E_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) sio_data->type = f71808e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) case SIO_F71808A_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) sio_data->type = f71808a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) case SIO_F71858_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) sio_data->type = f71858fg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) case SIO_F71862_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) sio_data->type = f71862fg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) case SIO_F71868_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) sio_data->type = f71868a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) case SIO_F71869_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) sio_data->type = f71869;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) case SIO_F71869A_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) sio_data->type = f71869a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) case SIO_F71882_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) sio_data->type = f71882fg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) case SIO_F71889_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) sio_data->type = f71889fg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) case SIO_F71889E_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) sio_data->type = f71889ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) case SIO_F71889A_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) sio_data->type = f71889a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) case SIO_F8000_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) sio_data->type = f8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) case SIO_F81768D_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) sio_data->type = f81768d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) case SIO_F81865_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) sio_data->type = f81865f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) case SIO_F81866_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) sio_data->type = f81866a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) pr_info("Unsupported Fintek device: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) (unsigned int)devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if (sio_data->type == f71858fg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) superio_select(sioaddr, SIO_F71858FG_LD_HWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) superio_select(sioaddr, SIO_F71882FG_LD_HWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) if (!(superio_inb(sioaddr, SIO_REG_ENABLE) & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) pr_warn("Device not activated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) address = superio_inw(sioaddr, SIO_REG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) if (address == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) pr_warn("Base address not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) address &= ~(REGION_LENGTH - 1); /* Ignore 3 LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) err = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) pr_info("Found %s chip at %#x, revision %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) f71882fg_names[sio_data->type], (unsigned int)address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) (int)superio_inb(sioaddr, SIO_REG_DEVREV));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) superio_exit(sioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static int __init f71882fg_device_add(int address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) const struct f71882fg_sio_data *sio_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) struct resource res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .start = address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .end = address + REGION_LENGTH - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) f71882fg_pdev = platform_device_alloc(DRVNAME, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (!f71882fg_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) res.name = f71882fg_pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) err = acpi_check_resource_conflict(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) err = platform_device_add_resources(f71882fg_pdev, &res, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) pr_err("Device resource addition failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) err = platform_device_add_data(f71882fg_pdev, sio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) sizeof(struct f71882fg_sio_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) pr_err("Platform data allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) err = platform_device_add(f71882fg_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) pr_err("Device addition failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) exit_device_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) platform_device_put(f71882fg_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static int __init f71882fg_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) struct f71882fg_sio_data sio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) memset(&sio_data, 0, sizeof(sio_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) address = f71882fg_find(0x2e, &sio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) if (address < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) address = f71882fg_find(0x4e, &sio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (address < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) err = platform_driver_register(&f71882fg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) err = f71882fg_device_add(address, &sio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) goto exit_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) exit_driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) platform_driver_unregister(&f71882fg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) static void __exit f71882fg_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) platform_device_unregister(f71882fg_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) platform_driver_unregister(&f71882fg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) MODULE_DESCRIPTION("F71882FG Hardware Monitoring Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) MODULE_AUTHOR("Hans Edgington, Hans de Goede <hdegoede@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) module_init(f71882fg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) module_exit(f71882fg_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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