^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * and SCH5127 Super-I/O chips integrated hardware monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * if a SCH311x or SCH5127 chip is found. Both types of chips have very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * similar hardware monitoring capabilities but differ in the way they can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * accessed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/hwmon-vid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* ISA device, if found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Module load parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static bool force_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) module_param(force_start, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static unsigned short force_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) module_param(force_id, ushort, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_PARM_DESC(force_id, "Override the detected device ID");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static bool probe_all_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) module_param(probe_all_addr, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_PARM_DESC(probe_all_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "Include probing of non-standard LPC addresses");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Addresses to scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum chips { dme1737, sch5027, sch311x, sch5127 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DO_REPORT "Please report to the driver maintainer."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The sensors are defined as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Voltages Temperatures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * -------- ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * in0 +5VTR (+5V stdby) temp1 Remote diode 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * in1 Vccp (proc core) temp2 Internal temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * in2 VCC (internal +3.3V) temp3 Remote diode 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * in3 +5V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * in4 +12V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * in5 VTR (+3.3V stby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * in6 Vbat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * in7 Vtrip (sch5127 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Voltages (in) numbered 0-7 (ix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (ix) < 7 ? 0x94 + (ix) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) : 0x91 + (ix) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) : 0x92 + (ix) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Temperatures (temp) numbered 0-2 (ix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DME1737_REG_TEMP(ix) (0x25 + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) : 0x1c + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Voltage and temperature LSBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * IN_TEMP_LSB(0) = [in5, in6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * IN_TEMP_LSB(1) = [temp3, temp1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * IN_TEMP_LSB(2) = [in4, temp2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * IN_TEMP_LSB(3) = [in3, in0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * IN_TEMP_LSB(4) = [in2, in1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * IN_TEMP_LSB(5) = [res, in7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Fans numbered 0-5 (ix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) : 0xa1 + (ix) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) : 0xa5 + (ix) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) : 0xb2 + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* PWMs numbered 0-2, 4-5 (ix) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) : 0xa1 + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) : 0xa3 + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * The layout of the ramp rate registers is different from the other pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * registers. The bits for the 3 PWMs are stored in 2 registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Thermal zones 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * The layout of the hysteresis registers is different from the other zone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * registers. The bits for the 3 zones are stored in 2 registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Alarm registers and bit mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * The 3 8-bit alarm registers will be concatenated to a single 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * alarm value [0, ALARM3, ALARM2, ALARM1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DME1737_REG_ALARM1 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DME1737_REG_ALARM2 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DME1737_REG_ALARM3 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Miscellaneous registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DME1737_REG_DEVICE 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DME1737_REG_COMPANY 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DME1737_REG_VERSTEP 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DME1737_REG_CONFIG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DME1737_REG_CONFIG2 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DME1737_REG_VID 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DME1737_REG_TACH_PWM 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Misc defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Chip identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DME1737_COMPANY_SMSC 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DME1737_VERSTEP 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DME1737_VERSTEP_MASK 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SCH311X_DEVICE 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SCH5027_VERSTEP 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SCH5127_DEVICE 0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Device ID values (global configuration register index 0x20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DME1737_ID_1 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DME1737_ID_2 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SCH3112_ID 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SCH3114_ID 0x7d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SCH3116_ID 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SCH5027_ID 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SCH5127_ID 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Length of ISA address segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DME1737_EXTENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* chip-dependent features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HAS_VID (1 << 1) /* bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HAS_ZONE3 (1 << 2) /* bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HAS_ZONE_HYST (1 << 3) /* bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HAS_PWM_MIN (1 << 4) /* bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HAS_IN7 (1 << 17) /* bit 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Data structures and manipulation thereof
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct dme1737_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct i2c_client *client; /* for I2C devices only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int addr; /* for ISA devices only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int valid; /* !=0 if following fields are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long last_update; /* in jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long last_vbat; /* in jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum chips type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const int *in_nominal; /* pointer to IN_NOMINAL array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 pwm_rr_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 has_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 in[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 in_min[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 in_max[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) s16 temp[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) s8 temp_min[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) s8 temp_max[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) s8 temp_offset[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 vrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u16 fan[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u16 fan_min[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 fan_max[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 fan_opt[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 pwm[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 pwm_min[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 pwm_config[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 pwm_acz[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 pwm_freq[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 pwm_rr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) s8 zone_low[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) s8 zone_abs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 zone_hyst[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Nominal voltage values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 3300};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 3300};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 3300};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 3300, 1500};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) IN_NOMINAL_DME1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Voltage input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Voltage inputs have 16 bits resolution, limit values have 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline int IN_FROM_REG(int reg, int nominal, int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static inline int IN_TO_REG(long val, int nominal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val = clamp_val(val, 0, 255 * nominal / 192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return DIV_ROUND_CLOSEST(val * 192, nominal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Temperature input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * The register values represent temperatures in 2's complement notation from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * values have 8 bits resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static inline int TEMP_FROM_REG(int reg, int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return (reg * 1000) >> (res - 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline int TEMP_TO_REG(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val = clamp_val(val, -128000, 127000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return DIV_ROUND_CLOSEST(val, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Temperature range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 10000, 13333, 16000, 20000, 26666, 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 40000, 53333, 80000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static inline int TEMP_RANGE_FROM_REG(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return TEMP_RANGE[(reg >> 4) & 0x0f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int TEMP_RANGE_TO_REG(long val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 15; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return (reg & 0x0f) | (i << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Temperature hysteresis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Register layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static inline int TEMP_HYST_FROM_REG(int reg, int ix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static inline int TEMP_HYST_TO_REG(int temp, long hyst, int ix, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hyst = clamp_val(hyst, temp - 15000, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) hyst = DIV_ROUND_CLOSEST(temp - hyst, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Fan input RPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline int FAN_FROM_REG(int reg, int tpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (tpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return tpc * reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static inline int FAN_TO_REG(long val, int tpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (tpc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return clamp_val(val / tpc, 0, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return (val <= 0) ? 0xffff :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clamp_val(90000 * 60 / val, 0, 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Fan TPC (tach pulse count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Converts a register value to a TPC multiplier or returns 0 if the tachometer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * is configured in legacy (non-tpc) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static inline int FAN_TPC_FROM_REG(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Fan type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * The type of a fan is expressed in number of pulses-per-revolution that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * emits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static inline int FAN_TYPE_FROM_REG(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int edge = (reg >> 1) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return (edge > 0) ? 1 << (edge - 1) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline int FAN_TYPE_TO_REG(long val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int edge = (val == 4) ? 3 : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return (reg & 0xf9) | (edge << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Fan max RPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x11, 0x0f, 0x0e};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int FAN_MAX_FROM_REG(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 10; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (reg == FAN_MAX[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 1000 + i * 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int FAN_MAX_TO_REG(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) for (i = 10; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (val > (1000 + (i - 1) * 500))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return FAN_MAX[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * PWM enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Register to enable mapping:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * 000: 2 fan on zone 1 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * 001: 2 fan on zone 2 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * 010: 2 fan on zone 3 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * 011: 0 fan full on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * 100: -1 fan disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * 101: 2 fan on hottest of zones 2,3 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * 110: 2 fan on hottest of zones 1,2,3 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * 111: 1 fan in manual mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static inline int PWM_EN_FROM_REG(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return en[(reg >> 5) & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static inline int PWM_EN_TO_REG(int val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int en = (val == 1) ? 7 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return (reg & 0x1f) | ((en & 0x07) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * PWM auto channels zone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Register to auto channels zone mapping (ACZ is a bitfield with bit x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * corresponding to zone x+1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * 000: 001 fan on zone 1 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * 001: 010 fan on zone 2 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * 010: 100 fan on zone 3 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * 011: 000 fan full on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * 100: 000 fan disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * 101: 110 fan on hottest of zones 2,3 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * 110: 111 fan on hottest of zones 1,2,3 auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * 111: 000 fan in manual mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline int PWM_ACZ_FROM_REG(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return acz[(reg >> 5) & 0x07];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static inline int PWM_ACZ_TO_REG(long val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int acz = (val == 4) ? 2 : val - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return (reg & 0x1f) | ((acz & 0x07) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* PWM frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 15000, 20000, 30000, 25000, 0, 0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static inline int PWM_FREQ_FROM_REG(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return PWM_FREQ[reg & 0x0f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int PWM_FREQ_TO_REG(long val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* the first two cases are special - stupid chip design! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (val > 27500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) i = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else if (val > 22500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) for (i = 9; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return (reg & 0xf0) | i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * PWM ramp rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Register layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static inline int PWM_RR_FROM_REG(int reg, int ix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int rr = (ix == 1) ? reg >> 4 : reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int PWM_RR_TO_REG(long val, int ix, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* PWM ramp rate enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static inline int PWM_RR_EN_TO_REG(long val, int ix, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int en = (ix == 1) ? 0x80 : 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return val ? reg | en : reg & ~en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * PWM min/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * the register layout).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static inline int PWM_OFF_FROM_REG(int reg, int ix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return (reg >> (ix + 5)) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Device I/O access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * ISA access is performed through an index/data register pair and needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * be protected by a mutex during runtime (not required for initialization).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * We use data->update_lock for this and need to ensure that we acquire it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * before calling dme1737_read or dme1737_write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) s32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (client) { /* I2C device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) val = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "Read from register 0x%02x failed! %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) reg, DO_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } else { /* ISA device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) outb(reg, data->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) val = inb(data->addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) s32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (client) { /* I2C device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) res = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "Write to register 0x%02x failed! %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) reg, DO_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } else { /* ISA device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) outb(reg, data->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) outb(val, data->addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct dme1737_data *dme1737_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 lsb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Enable a Vbat monitoring cycle every 10 mins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DME1737_REG_CONFIG) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) data->last_vbat = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Sample register contents every 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (data->has_features & HAS_VID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) data->vid = dme1737_read(data, DME1737_REG_VID) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* In (voltage) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * Voltage inputs are stored as 16 bit values even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * though they have only 12 bits resolution. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * to make it consistent with the temp inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ix == 7 && !(data->has_features & HAS_IN7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) data->in[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) DME1737_REG_IN(ix)) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) data->in_min[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) DME1737_REG_IN_MIN(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) data->in_max[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DME1737_REG_IN_MAX(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Temp registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * Temp inputs are stored as 16 bit values even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * though they have only 12 bits resolution. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * to take advantage of implicit conversions between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * register values (2's complement) and temp values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * (signed decimal).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) data->temp[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) DME1737_REG_TEMP(ix)) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) data->temp_min[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) DME1737_REG_TEMP_MIN(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) data->temp_max[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) DME1737_REG_TEMP_MAX(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (data->has_features & HAS_TEMP_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) data->temp_offset[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) DME1737_REG_TEMP_OFFSET(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * In and temp LSB registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * The LSBs are latched when the MSBs are read, so the order in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * which the registers are read (MSB first, then LSB) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * important!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ix == 5 && !(data->has_features & HAS_IN7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) lsb[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) DME1737_REG_IN_TEMP_LSB(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ix == 7 && !(data->has_features & HAS_IN7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Fan registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Skip reading registers if optional fans are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!(data->has_features & HAS_FAN(ix)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) data->fan[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) DME1737_REG_FAN(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) data->fan[ix] |= dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) DME1737_REG_FAN(ix) + 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) data->fan_min[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) DME1737_REG_FAN_MIN(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) data->fan_min[ix] |= dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) DME1737_REG_FAN_MIN(ix) + 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) data->fan_opt[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DME1737_REG_FAN_OPT(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* fan_max exists only for fan[5-6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ix > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) data->fan_max[ix - 4] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) DME1737_REG_FAN_MAX(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* PWM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Skip reading registers if optional PWMs are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!(data->has_features & HAS_PWM(ix)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) data->pwm[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DME1737_REG_PWM(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) data->pwm_freq[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) DME1737_REG_PWM_FREQ(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* pwm_config and pwm_min exist only for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ix < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) data->pwm_config[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) DME1737_REG_PWM_CONFIG(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) data->pwm_min[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) DME1737_REG_PWM_MIN(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) data->pwm_rr[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) DME1737_REG_PWM_RR(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Thermal zone registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Skip reading registers if zone3 is not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if ((ix == 2) && !(data->has_features & HAS_ZONE3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* sch5127 zone2 registers are special */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if ((ix == 1) && (data->type == sch5127)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) data->zone_low[1] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DME1737_REG_ZONE_LOW(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) data->zone_abs[1] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) DME1737_REG_ZONE_ABS(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) data->zone_low[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) DME1737_REG_ZONE_LOW(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) data->zone_abs[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) DME1737_REG_ZONE_ABS(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (data->has_features & HAS_ZONE_HYST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) data->zone_hyst[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) DME1737_REG_ZONE_HYST(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* Alarm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) data->alarms = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) DME1737_REG_ALARM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Bit 7 tells us if the other alarm registers are non-zero and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * therefore also need to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (data->alarms & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) data->alarms |= dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) DME1737_REG_ALARM2) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) data->alarms |= dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) DME1737_REG_ALARM3) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * The ISA chips require explicit clearing of alarm bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Don't worry, an alarm will come back if the condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * that causes it still exists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!data->client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (data->alarms & 0xff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dme1737_write(data, DME1737_REG_ALARM3, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (data->alarms & 0xff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dme1737_write(data, DME1737_REG_ALARM2, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (data->alarms & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dme1737_write(data, DME1737_REG_ALARM1, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) data->last_update = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) data->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Voltage sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * ix = [0-7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define SYS_IN_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define SYS_IN_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SYS_IN_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SYS_IN_ALARM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static ssize_t show_in(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct dme1737_data *data = dme1737_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case SYS_IN_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case SYS_IN_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case SYS_IN_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case SYS_IN_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return sprintf(buf, "%d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static ssize_t set_in(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case SYS_IN_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dme1737_write(data, DME1737_REG_IN_MIN(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) data->in_min[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case SYS_IN_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dme1737_write(data, DME1737_REG_IN_MAX(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) data->in_max[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * Temperature sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * ix = [0-2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define SYS_TEMP_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define SYS_TEMP_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define SYS_TEMP_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define SYS_TEMP_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define SYS_TEMP_ALARM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define SYS_TEMP_FAULT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct dme1737_data *data = dme1737_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case SYS_TEMP_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) res = TEMP_FROM_REG(data->temp[ix], 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case SYS_TEMP_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) res = TEMP_FROM_REG(data->temp_min[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case SYS_TEMP_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) res = TEMP_FROM_REG(data->temp_max[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case SYS_TEMP_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) res = TEMP_FROM_REG(data->temp_offset[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case SYS_TEMP_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case SYS_TEMP_FAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return sprintf(buf, "%d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case SYS_TEMP_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) data->temp_min[ix] = TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) data->temp_min[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case SYS_TEMP_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) data->temp_max[ix] = TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) data->temp_max[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case SYS_TEMP_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) data->temp_offset[ix] = TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) data->temp_offset[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * Zone sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * ix = [0-2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define SYS_ZONE_AUTO_CHANNELS_TEMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define SYS_ZONE_AUTO_POINT1_TEMP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define SYS_ZONE_AUTO_POINT2_TEMP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define SYS_ZONE_AUTO_POINT3_TEMP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct dme1737_data *data = dme1737_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case SYS_ZONE_AUTO_CHANNELS_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* check config2 for non-standard temp-to-zone mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if ((ix == 1) && (data->config2 & 0x02))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) res = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) res = 1 << ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) res = TEMP_FROM_REG(data->zone_low[ix], 8) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) case SYS_ZONE_AUTO_POINT1_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) res = TEMP_FROM_REG(data->zone_low[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case SYS_ZONE_AUTO_POINT2_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* pwm_freq holds the temp range bits in the upper nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) res = TEMP_FROM_REG(data->zone_low[ix], 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) case SYS_ZONE_AUTO_POINT3_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) res = TEMP_FROM_REG(data->zone_abs[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return sprintf(buf, "%d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Refresh the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) data->zone_low[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) DME1737_REG_ZONE_LOW(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Modify the temp hyst value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) temp = TEMP_FROM_REG(data->zone_low[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) reg = dme1737_read(data, DME1737_REG_ZONE_HYST(ix == 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(temp, val, ix, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) data->zone_hyst[ix == 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case SYS_ZONE_AUTO_POINT1_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) data->zone_low[ix] = TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) data->zone_low[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case SYS_ZONE_AUTO_POINT2_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Refresh the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) data->zone_low[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) DME1737_REG_ZONE_LOW(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * Modify the temp range value (which is stored in the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * nibble of the pwm_freq register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) temp = TEMP_FROM_REG(data->zone_low[ix], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) val = clamp_val(val, temp, temp + 80000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) reg = dme1737_read(data, DME1737_REG_PWM_FREQ(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - temp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) data->pwm_freq[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) case SYS_ZONE_AUTO_POINT3_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) data->zone_abs[ix] = TEMP_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) data->zone_abs[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * Fan sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * ix = [0-5]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define SYS_FAN_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define SYS_FAN_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define SYS_FAN_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define SYS_FAN_ALARM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define SYS_FAN_TYPE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct dme1737_data *data = dme1737_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case SYS_FAN_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) res = FAN_FROM_REG(data->fan[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ix < 4 ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) FAN_TPC_FROM_REG(data->fan_opt[ix]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) case SYS_FAN_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) res = FAN_FROM_REG(data->fan_min[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ix < 4 ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) FAN_TPC_FROM_REG(data->fan_opt[ix]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case SYS_FAN_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* only valid for fan[5-6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case SYS_FAN_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case SYS_FAN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* only valid for fan[1-4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return sprintf(buf, "%d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) case SYS_FAN_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ix < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) data->fan_min[ix] = FAN_TO_REG(val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Refresh the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) data->fan_opt[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) DME1737_REG_FAN_OPT(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* Modify the fan min value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) data->fan_min[ix] = FAN_TO_REG(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) FAN_TPC_FROM_REG(data->fan_opt[ix]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dme1737_write(data, DME1737_REG_FAN_MIN(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) data->fan_min[ix] & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) data->fan_min[ix] >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) case SYS_FAN_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* Only valid for fan[5-6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dme1737_write(data, DME1737_REG_FAN_MAX(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) data->fan_max[ix - 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) case SYS_FAN_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Only valid for fan[1-4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (!(val == 1 || val == 2 || val == 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "Fan type value %ld not supported. Choose one of 1, 2, or 4.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) DME1737_REG_FAN_OPT(ix)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dme1737_write(data, DME1737_REG_FAN_OPT(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) data->fan_opt[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * PWM sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * ix = [0-4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define SYS_PWM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define SYS_PWM_FREQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define SYS_PWM_ENABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define SYS_PWM_RAMP_RATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define SYS_PWM_AUTO_CHANNELS_ZONE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define SYS_PWM_AUTO_PWM_MIN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define SYS_PWM_AUTO_POINT1_PWM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define SYS_PWM_AUTO_POINT2_PWM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct dme1737_data *data = dme1737_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) case SYS_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) res = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) res = data->pwm[ix];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) case SYS_PWM_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case SYS_PWM_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (ix >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) res = 1; /* pwm[5-6] hard-wired to manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) res = PWM_EN_FROM_REG(data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case SYS_PWM_RAMP_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case SYS_PWM_AUTO_CHANNELS_ZONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) res = data->pwm_acz[ix];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) case SYS_PWM_AUTO_PWM_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) res = data->pwm_min[ix];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) case SYS_PWM_AUTO_POINT1_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) res = data->pwm_min[ix];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case SYS_PWM_AUTO_POINT2_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) res = 255; /* hard-wired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return sprintf(buf, "%d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static struct attribute *dme1737_pwm_chmod_attr[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static void dme1737_chmod_file(struct device*, struct attribute*, umode_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct sensor_device_attribute_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) *sensor_attr_2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) int ix = sensor_attr_2->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) int fn = sensor_attr_2->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) switch (fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) case SYS_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) data->pwm[ix] = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case SYS_PWM_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) DME1737_REG_PWM_FREQ(ix)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) data->pwm_freq[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case SYS_PWM_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (val < 0 || val > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) "PWM enable %ld not supported. Choose one of 0, 1, or 2.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* Refresh the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) data->pwm_config[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) DME1737_REG_PWM_CONFIG(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* Bail out if no change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* Do some housekeeping if we are currently in auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* Save the current zone channel assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* Save the current ramp rate state and disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) data->pwm_rr[ix > 0] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) DME1737_REG_PWM_RR(ix > 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) data->pwm_rr_en &= ~(1 << ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) data->pwm_rr_en |= (1 << ix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) data->pwm_rr[ix > 0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dme1737_write(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) DME1737_REG_PWM_RR(ix > 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) data->pwm_rr[ix > 0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Set the new PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Change permissions of pwm[ix] to read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Turn fan fully on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) data->pwm_config[ix] = PWM_EN_TO_REG(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* Turn on manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) data->pwm_config[ix] = PWM_EN_TO_REG(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* Change permissions of pwm[ix] to read-writeable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /* Change permissions of pwm[ix] to read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * Turn on auto mode using the saved zone channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) data->pwm_config[ix] = PWM_ACZ_TO_REG(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) data->pwm_acz[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* Enable PWM ramp rate if previously enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (data->pwm_rr_en & (1 << ix)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) DME1737_REG_PWM_RR(ix > 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) dme1737_write(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) DME1737_REG_PWM_RR(ix > 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) data->pwm_rr[ix > 0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) case SYS_PWM_RAMP_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Refresh the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) data->pwm_config[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) DME1737_REG_PWM_CONFIG(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) data->pwm_rr[ix > 0] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) DME1737_REG_PWM_RR(ix > 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* Set the ramp rate value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (val > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) data->pwm_rr[ix > 0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * Enable/disable the feature only if the associated PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * output is in automatic mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) data->pwm_rr[ix > 0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) data->pwm_rr[ix > 0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case SYS_PWM_AUTO_CHANNELS_ZONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (!(val == 1 || val == 2 || val == 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) val == 6 || val == 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) "PWM auto channels zone %ld not supported. Choose one of 1, 2, 4, 6, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) "or 7.\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* Refresh the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) data->pwm_config[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) DME1737_REG_PWM_CONFIG(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * PWM is already in auto mode so update the temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * channel assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * PWM is not in auto mode so we save the temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * channel assignment for later use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) data->pwm_acz[ix] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) case SYS_PWM_AUTO_PWM_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* Refresh the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) data->pwm_min[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) DME1737_REG_PWM_MIN(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * There are only 2 values supported for the auto_pwm_min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * value: 0 or auto_point1_pwm. So if the temperature drops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * below the auto_point1_temp_hyst value, the fan either turns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * off or runs at auto_point1_pwm duty-cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (val > ((data->pwm_min[ix] + 1) / 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) DME1737_REG_PWM_RR(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) DME1737_REG_PWM_RR(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) dme1737_write(data, DME1737_REG_PWM_RR(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) data->pwm_rr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) case SYS_PWM_AUTO_POINT1_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* Only valid for pwm[1-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) data->pwm_min[ix] = clamp_val(val, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dme1737_write(data, DME1737_REG_PWM_MIN(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) data->pwm_min[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev_dbg(dev, "Unknown function %d.\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * Miscellaneous sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct dme1737_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return sprintf(buf, "%d\n", data->vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) err = kstrtoul(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (val > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) data->vrm = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static ssize_t cpu0_vid_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct dme1737_data *data = dme1737_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static ssize_t name_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return sprintf(buf, "%s\n", data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * Sysfs device attribute defines and structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* Voltages 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define SENSOR_DEVICE_ATTR_IN(ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) show_in, NULL, SYS_IN_INPUT, ix); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) show_in, set_in, SYS_IN_MIN, ix); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) show_in, set_in, SYS_IN_MAX, ix); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) show_in, NULL, SYS_IN_ALARM, ix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) SENSOR_DEVICE_ATTR_IN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) SENSOR_DEVICE_ATTR_IN(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) SENSOR_DEVICE_ATTR_IN(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SENSOR_DEVICE_ATTR_IN(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SENSOR_DEVICE_ATTR_IN(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SENSOR_DEVICE_ATTR_IN(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) SENSOR_DEVICE_ATTR_IN(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) SENSOR_DEVICE_ATTR_IN(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* Temperatures 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define SENSOR_DEVICE_ATTR_TEMP(ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) show_temp, NULL, SYS_TEMP_FAULT, ix-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SENSOR_DEVICE_ATTR_TEMP(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) SENSOR_DEVICE_ATTR_TEMP(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) SENSOR_DEVICE_ATTR_TEMP(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* Zones 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define SENSOR_DEVICE_ATTR_ZONE(ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) SENSOR_DEVICE_ATTR_ZONE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) SENSOR_DEVICE_ATTR_ZONE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) SENSOR_DEVICE_ATTR_ZONE(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Fans 1-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) show_fan, NULL, SYS_FAN_INPUT, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) show_fan, set_fan, SYS_FAN_MIN, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) show_fan, NULL, SYS_FAN_ALARM, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) show_fan, set_fan, SYS_FAN_TYPE, ix-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) SENSOR_DEVICE_ATTR_FAN_1TO4(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) SENSOR_DEVICE_ATTR_FAN_1TO4(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) SENSOR_DEVICE_ATTR_FAN_1TO4(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) SENSOR_DEVICE_ATTR_FAN_1TO4(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* Fans 5-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) show_fan, NULL, SYS_FAN_INPUT, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) show_fan, set_fan, SYS_FAN_MIN, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) show_fan, NULL, SYS_FAN_ALARM, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) show_fan, set_fan, SYS_FAN_MAX, ix-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) SENSOR_DEVICE_ATTR_FAN_5TO6(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) SENSOR_DEVICE_ATTR_FAN_5TO6(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* PWMs 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) show_pwm, set_pwm, SYS_PWM, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) SENSOR_DEVICE_ATTR_PWM_1TO3(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) SENSOR_DEVICE_ATTR_PWM_1TO3(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) SENSOR_DEVICE_ATTR_PWM_1TO3(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* PWMs 5-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) show_pwm, set_pwm, SYS_PWM, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) SENSOR_DEVICE_ATTR_PWM_5TO6(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) SENSOR_DEVICE_ATTR_PWM_5TO6(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static DEVICE_ATTR_RW(vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static DEVICE_ATTR_RO(cpu0_vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static DEVICE_ATTR_RO(name); /* for ISA devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * This struct holds all the attributes that are always present and need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * created unconditionally. The attributes that need modification of their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * permissions are created read-only and write permissions are added or removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * on the fly when required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static struct attribute *dme1737_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* Voltages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) &sensor_dev_attr_in0_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) &sensor_dev_attr_in0_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) &sensor_dev_attr_in0_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) &sensor_dev_attr_in0_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) &sensor_dev_attr_in1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) &sensor_dev_attr_in1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) &sensor_dev_attr_in1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) &sensor_dev_attr_in1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) &sensor_dev_attr_in2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) &sensor_dev_attr_in2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) &sensor_dev_attr_in2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) &sensor_dev_attr_in2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) &sensor_dev_attr_in3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) &sensor_dev_attr_in3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) &sensor_dev_attr_in3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) &sensor_dev_attr_in3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) &sensor_dev_attr_in4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) &sensor_dev_attr_in4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) &sensor_dev_attr_in4_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) &sensor_dev_attr_in4_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) &sensor_dev_attr_in5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) &sensor_dev_attr_in5_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) &sensor_dev_attr_in5_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) &sensor_dev_attr_in5_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) &sensor_dev_attr_in6_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) &sensor_dev_attr_in6_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) &sensor_dev_attr_in6_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) &sensor_dev_attr_in6_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* Temperatures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) &sensor_dev_attr_temp1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) &sensor_dev_attr_temp1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) &sensor_dev_attr_temp1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) &sensor_dev_attr_temp1_fault.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) &sensor_dev_attr_temp2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) &sensor_dev_attr_temp2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) &sensor_dev_attr_temp2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) &sensor_dev_attr_temp2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) &sensor_dev_attr_temp2_fault.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) &sensor_dev_attr_temp3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) &sensor_dev_attr_temp3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) &sensor_dev_attr_temp3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) &sensor_dev_attr_temp3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) &sensor_dev_attr_temp3_fault.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* Zones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const struct attribute_group dme1737_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .attrs = dme1737_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * The following struct holds temp offset attributes, which are not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * in all chips. The following chips support them:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * DME1737, SCH311x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static struct attribute *dme1737_temp_offset_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) &sensor_dev_attr_temp1_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) &sensor_dev_attr_temp2_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) &sensor_dev_attr_temp3_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static const struct attribute_group dme1737_temp_offset_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .attrs = dme1737_temp_offset_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) * The following struct holds VID related attributes, which are not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * in all chips. The following chips support them:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) * DME1737
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static struct attribute *dme1737_vid_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) &dev_attr_vrm.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) &dev_attr_cpu0_vid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static const struct attribute_group dme1737_vid_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .attrs = dme1737_vid_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * The following struct holds temp zone 3 related attributes, which are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * available in all chips. The following chips support them:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * DME1737, SCH311x, SCH5027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static struct attribute *dme1737_zone3_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static const struct attribute_group dme1737_zone3_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .attrs = dme1737_zone3_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * The following struct holds temp zone hysteresis related attributes, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * are not available in all chips. The following chips support them:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * DME1737, SCH311x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static struct attribute *dme1737_zone_hyst_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static const struct attribute_group dme1737_zone_hyst_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .attrs = dme1737_zone_hyst_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * The following struct holds voltage in7 related attributes, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * are not available in all chips. The following chips support them:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) * SCH5127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static struct attribute *dme1737_in7_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) &sensor_dev_attr_in7_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) &sensor_dev_attr_in7_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) &sensor_dev_attr_in7_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) &sensor_dev_attr_in7_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static const struct attribute_group dme1737_in7_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .attrs = dme1737_in7_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * The following structs hold the PWM attributes, some of which are optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * Their creation depends on the chip configuration which is determined during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * module load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static struct attribute *dme1737_pwm1_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) &sensor_dev_attr_pwm1.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) &sensor_dev_attr_pwm1_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) &sensor_dev_attr_pwm1_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static struct attribute *dme1737_pwm2_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) &sensor_dev_attr_pwm2.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) &sensor_dev_attr_pwm2_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) &sensor_dev_attr_pwm2_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static struct attribute *dme1737_pwm3_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) &sensor_dev_attr_pwm3.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) &sensor_dev_attr_pwm3_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) &sensor_dev_attr_pwm3_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static struct attribute *dme1737_pwm5_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) &sensor_dev_attr_pwm5.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) &sensor_dev_attr_pwm5_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) &sensor_dev_attr_pwm5_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static struct attribute *dme1737_pwm6_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) &sensor_dev_attr_pwm6.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) &sensor_dev_attr_pwm6_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) &sensor_dev_attr_pwm6_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static const struct attribute_group dme1737_pwm_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) { .attrs = dme1737_pwm1_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) { .attrs = dme1737_pwm2_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) { .attrs = dme1737_pwm3_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) { .attrs = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) { .attrs = dme1737_pwm5_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) { .attrs = dme1737_pwm6_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) * The following struct holds auto PWM min attributes, which are not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) * in all chips. Their creation depends on the chip type which is determined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) * during module load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static struct attribute *dme1737_auto_pwm_min_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * The following structs hold the fan attributes, some of which are optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * Their creation depends on the chip configuration which is determined during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * module load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static struct attribute *dme1737_fan1_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) &sensor_dev_attr_fan1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) &sensor_dev_attr_fan1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) &sensor_dev_attr_fan1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) &sensor_dev_attr_fan1_type.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static struct attribute *dme1737_fan2_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) &sensor_dev_attr_fan2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) &sensor_dev_attr_fan2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) &sensor_dev_attr_fan2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) &sensor_dev_attr_fan2_type.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static struct attribute *dme1737_fan3_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) &sensor_dev_attr_fan3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) &sensor_dev_attr_fan3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) &sensor_dev_attr_fan3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) &sensor_dev_attr_fan3_type.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static struct attribute *dme1737_fan4_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) &sensor_dev_attr_fan4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) &sensor_dev_attr_fan4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) &sensor_dev_attr_fan4_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) &sensor_dev_attr_fan4_type.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static struct attribute *dme1737_fan5_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) &sensor_dev_attr_fan5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) &sensor_dev_attr_fan5_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) &sensor_dev_attr_fan5_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) &sensor_dev_attr_fan5_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static struct attribute *dme1737_fan6_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) &sensor_dev_attr_fan6_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) &sensor_dev_attr_fan6_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) &sensor_dev_attr_fan6_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) &sensor_dev_attr_fan6_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) static const struct attribute_group dme1737_fan_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) { .attrs = dme1737_fan1_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) { .attrs = dme1737_fan2_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) { .attrs = dme1737_fan3_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) { .attrs = dme1737_fan4_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) { .attrs = dme1737_fan5_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) { .attrs = dme1737_fan6_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) * The permissions of the following zone attributes are changed to read-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) * writeable if the chip is *not* locked. Otherwise they stay read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static struct attribute *dme1737_zone_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static const struct attribute_group dme1737_zone_chmod_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .attrs = dme1737_zone_chmod_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * The permissions of the following zone 3 attributes are changed to read-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * writeable if the chip is *not* locked. Otherwise they stay read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static struct attribute *dme1737_zone3_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static const struct attribute_group dme1737_zone3_chmod_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .attrs = dme1737_zone3_chmod_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * The permissions of the following PWM attributes are changed to read-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * writeable if the chip is *not* locked and the respective PWM is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * Otherwise they stay read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) static struct attribute *dme1737_pwm1_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) &sensor_dev_attr_pwm1_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) &sensor_dev_attr_pwm1_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static struct attribute *dme1737_pwm2_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) &sensor_dev_attr_pwm2_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) &sensor_dev_attr_pwm2_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static struct attribute *dme1737_pwm3_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) &sensor_dev_attr_pwm3_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) &sensor_dev_attr_pwm3_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static struct attribute *dme1737_pwm5_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) &sensor_dev_attr_pwm5.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) &sensor_dev_attr_pwm5_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static struct attribute *dme1737_pwm6_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) &sensor_dev_attr_pwm6.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) &sensor_dev_attr_pwm6_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) static const struct attribute_group dme1737_pwm_chmod_group[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) { .attrs = dme1737_pwm1_chmod_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) { .attrs = dme1737_pwm2_chmod_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) { .attrs = dme1737_pwm3_chmod_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) { .attrs = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) { .attrs = dme1737_pwm5_chmod_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) { .attrs = dme1737_pwm6_chmod_attr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * chip is not locked. Otherwise they are read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static struct attribute *dme1737_pwm_chmod_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) &sensor_dev_attr_pwm1.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) &sensor_dev_attr_pwm2.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) &sensor_dev_attr_pwm3.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * Super-IO functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static inline void dme1737_sio_enter(int sio_cip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) outb(0x55, sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static inline void dme1737_sio_exit(int sio_cip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) outb(0xaa, sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static inline int dme1737_sio_inb(int sio_cip, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) outb(reg, sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) return inb(sio_cip + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) outb(reg, sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) outb(val, sio_cip + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * Device initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static int dme1737_i2c_get_features(int, struct dme1737_data*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static void dme1737_chmod_file(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) struct attribute *attr, umode_t mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) dev_warn(dev, "Failed to change permissions of %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) attr->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static void dme1737_chmod_group(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) const struct attribute_group *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) umode_t mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct attribute **attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) for (attr = group->attrs; *attr; attr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) dme1737_chmod_file(dev, *attr, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static void dme1737_remove_files(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) int ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (data->has_features & HAS_FAN(ix)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) sysfs_remove_group(&dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) &dme1737_fan_group[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (data->has_features & HAS_PWM(ix)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) sysfs_remove_group(&dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) &dme1737_pwm_group[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if ((data->has_features & HAS_PWM_MIN) && ix < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) sysfs_remove_file(&dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) dme1737_auto_pwm_min_attr[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (data->has_features & HAS_TEMP_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (data->has_features & HAS_VID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (data->has_features & HAS_ZONE3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (data->has_features & HAS_ZONE_HYST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (data->has_features & HAS_IN7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) sysfs_remove_group(&dev->kobj, &dme1737_in7_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) sysfs_remove_group(&dev->kobj, &dme1737_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (!data->client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static int dme1737_create_files(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) int err, ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) /* Create a name attribute for ISA devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (!data->client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /* Create standard sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) err = sysfs_create_group(&dev->kobj, &dme1737_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) /* Create chip-dependent sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (data->has_features & HAS_TEMP_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) err = sysfs_create_group(&dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) &dme1737_temp_offset_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (data->has_features & HAS_VID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) err = sysfs_create_group(&dev->kobj, &dme1737_vid_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (data->has_features & HAS_ZONE3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (data->has_features & HAS_ZONE_HYST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (data->has_features & HAS_IN7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) err = sysfs_create_group(&dev->kobj, &dme1737_in7_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) /* Create fan sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (data->has_features & HAS_FAN(ix)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) err = sysfs_create_group(&dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) &dme1737_fan_group[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* Create PWM sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (data->has_features & HAS_PWM(ix)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) err = sysfs_create_group(&dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) &dme1737_pwm_group[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) err = sysfs_create_file(&dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) dme1737_auto_pwm_min_attr[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) * Inform if the device is locked. Otherwise change the permissions of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) * selected attributes from read-only to read-writeable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (data->config & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) "Device is locked. Some attributes will be read-only.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* Change permissions of zone sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* Change permissions of chip-dependent sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) if (data->has_features & HAS_TEMP_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) dme1737_chmod_group(dev, &dme1737_temp_offset_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (data->has_features & HAS_ZONE3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) dme1737_chmod_group(dev, &dme1737_zone3_chmod_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (data->has_features & HAS_ZONE_HYST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) dme1737_chmod_group(dev, &dme1737_zone_hyst_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* Change permissions of PWM sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (data->has_features & HAS_PWM(ix)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) dme1737_chmod_group(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) &dme1737_pwm_chmod_group[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) if ((data->has_features & HAS_PWM_MIN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ix < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) dme1737_chmod_file(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) dme1737_auto_pwm_min_attr[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* Change permissions of pwm[1-3] if in manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) for (ix = 0; ix < 3; ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if ((data->has_features & HAS_PWM(ix)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) dme1737_chmod_file(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) dme1737_pwm_chmod_attr[ix],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) exit_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) dme1737_remove_files(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static int dme1737_init_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct dme1737_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) int ix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /* Point to the right nominal voltages array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) data->in_nominal = IN_NOMINAL(data->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) data->config = dme1737_read(data, DME1737_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) /* Inform if part is not monitoring/started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (!(data->config & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (!force_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) "Device is not monitoring. Use the force_start load parameter to override.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* Force monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) data->config |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) dme1737_write(data, DME1737_REG_CONFIG, data->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) /* Inform if part is not ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (!(data->config & 0x04)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) dev_err(dev, "Device is not ready.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * Determine which optional fan and pwm features are enabled (only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) * valid for I2C devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (client) { /* I2C chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /* Check if optional fan3 input is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (data->config2 & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) data->has_features |= HAS_FAN(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) * Fan4 and pwm3 are only available if the client's I2C address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) * is the default 0x2e. Otherwise the I/Os associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) * these functions are used for addr enable/select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (client->addr == 0x2e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) data->has_features |= HAS_FAN(3) | HAS_PWM(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * Determine which of the optional fan[5-6] and pwm[5-6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) * features are enabled. For this, we need to query the runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) * registers through the Super-IO LPC interface. Try both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) * config ports 0x2e and 0x4e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (dme1737_i2c_get_features(0x2e, data) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) dme1737_i2c_get_features(0x4e, data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) "Failed to query Super-IO for optional features.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) /* Fan[1-2] and pwm[1-2] are present in all chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* Chip-dependent features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) switch (data->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) case dme1737:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) HAS_ZONE_HYST | HAS_PWM_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) case sch311x:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) case sch5027:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) data->has_features |= HAS_ZONE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) case sch5127:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) (data->has_features & HAS_PWM(2)) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) (data->has_features & HAS_PWM(4)) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) (data->has_features & HAS_PWM(5)) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) (data->has_features & HAS_FAN(2)) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) (data->has_features & HAS_FAN(3)) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) (data->has_features & HAS_FAN(4)) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) (data->has_features & HAS_FAN(5)) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) reg = dme1737_read(data, DME1737_REG_TACH_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) /* Inform if fan-to-pwm mapping differs from the default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (client && reg != 0xa4) { /* I2C chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, fan4->pwm%d. %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) DO_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) } else if (!client && reg != 0x24) { /* ISA chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) ((reg >> 4) & 0x03) + 1, DO_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) * Switch pwm[1-3] to manual mode if they are currently disabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) * set the duty-cycles to 0% (which is identical to the PWMs being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) * disabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if (!(data->config & 0x02)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) for (ix = 0; ix < 3; ix++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) data->pwm_config[ix] = dme1737_read(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) DME1737_REG_PWM_CONFIG(ix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if ((data->has_features & HAS_PWM(ix)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) "Switching pwm%d to manual mode.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) ix + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) data->pwm_config[ix] = PWM_EN_TO_REG(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) dme1737_write(data, DME1737_REG_PWM(ix), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) dme1737_write(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) DME1737_REG_PWM_CONFIG(ix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) data->pwm_config[ix]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) /* Initialize the default PWM auto channels zone (acz) assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) /* Set VRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (data->has_features & HAS_VID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) data->vrm = vid_which_vrm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) * I2C device detection and registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) static struct i2c_driver dme1737_i2c_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) int err = 0, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) dme1737_sio_enter(sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * Check device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) * We currently know about two kinds of DME1737 and SCH5027.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) reg == SCH5027_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* Select logical device A (runtime registers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) dme1737_sio_outb(sio_cip, 0x07, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* Get the base address of the runtime registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) dme1737_sio_inb(sio_cip, 0x61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) * Read the runtime registers to determine which optional features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) * to '10' if the respective feature is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) data->has_features |= HAS_FAN(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) data->has_features |= HAS_PWM(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) data->has_features |= HAS_FAN(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) data->has_features |= HAS_PWM(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) dme1737_sio_exit(sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /* Return 0 if detection is successful, -ENODEV otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) static int dme1737_i2c_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) struct device *dev = &adapter->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) u8 company, verstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) if (company == DME1737_COMPANY_SMSC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) verstep == SCH5027_VERSTEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) name = "sch5027";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) } else if (company == DME1737_COMPANY_SMSC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) name = "dme1737";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) client->addr, verstep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) strlcpy(info->type, name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static const struct i2c_device_id dme1737_id[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static int dme1737_i2c_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) struct dme1737_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) data->type = i2c_match_id(dme1737_id, client)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) data->name = client->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) /* Initialize the DME1737 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) err = dme1737_init_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) dev_err(dev, "Failed to initialize device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* Create sysfs files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) err = dme1737_create_files(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) dev_err(dev, "Failed to create sysfs files.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) /* Register device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) data->hwmon_dev = hwmon_device_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (IS_ERR(data->hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) dev_err(dev, "Failed to register device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) err = PTR_ERR(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) goto exit_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) exit_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) dme1737_remove_files(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static int dme1737_i2c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) struct dme1737_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) hwmon_device_unregister(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) dme1737_remove_files(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) static const struct i2c_device_id dme1737_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) { "dme1737", dme1737 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) { "sch5027", sch5027 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) MODULE_DEVICE_TABLE(i2c, dme1737_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) static struct i2c_driver dme1737_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .name = "dme1737",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .probe_new = dme1737_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .remove = dme1737_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .id_table = dme1737_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .detect = dme1737_i2c_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) * ISA device detection and registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) int err = 0, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) unsigned short base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) dme1737_sio_enter(sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) * Check device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) reg == SCH5127_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) /* Select logical device A (runtime registers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) dme1737_sio_outb(sio_cip, 0x07, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* Get the base address of the runtime registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) dme1737_sio_inb(sio_cip, 0x61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) if (!base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) pr_err("Base address not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) * Access to the hwmon registers is through an index/data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) * pair located at offset 0x70/0x71.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) *addr = base_addr + 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) dme1737_sio_exit(sio_cip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static int __init dme1737_isa_device_add(unsigned short addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) struct resource res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .start = addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .end = addr + DME1737_EXTENT - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .name = "dme1737",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) err = acpi_check_resource_conflict(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) pdev = platform_device_alloc("dme1737", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) pr_err("Failed to allocate device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) err = platform_device_add_resources(pdev, &res, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) pr_err("Failed to add device resource (err = %d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) err = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) pr_err("Failed to add device (err = %d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) exit_device_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) static int dme1737_isa_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) u8 company, device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) struct dme1737_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) if (!devm_request_region(dev, res->start, DME1737_EXTENT, "dme1737")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) (unsigned short)res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) (unsigned short)res->start + DME1737_EXTENT - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) data->addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) /* Skip chip detection if module is loaded with force_id parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) switch (force_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) case SCH3112_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) case SCH3114_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) case SCH3116_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) data->type = sch311x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) case SCH5127_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) data->type = sch5127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) company = dme1737_read(data, DME1737_REG_COMPANY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) device = dme1737_read(data, DME1737_REG_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if ((company == DME1737_COMPANY_SMSC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) (device == SCH311X_DEVICE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) data->type = sch311x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) } else if ((company == DME1737_COMPANY_SMSC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) (device == SCH5127_DEVICE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) data->type = sch5127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (data->type == sch5127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) data->name = "sch5127";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) data->name = "sch311x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) /* Initialize the mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) dev_info(dev, "Found a %s chip at 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) /* Initialize the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) err = dme1737_init_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) dev_err(dev, "Failed to initialize device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /* Create sysfs files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) err = dme1737_create_files(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) dev_err(dev, "Failed to create sysfs files.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /* Register device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) data->hwmon_dev = hwmon_device_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (IS_ERR(data->hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) dev_err(dev, "Failed to register device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) err = PTR_ERR(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) goto exit_remove_files;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) exit_remove_files:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) dme1737_remove_files(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) static int dme1737_isa_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) struct dme1737_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) hwmon_device_unregister(data->hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) dme1737_remove_files(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) static struct platform_driver dme1737_isa_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .name = "dme1737",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .probe = dme1737_isa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .remove = dme1737_isa_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) * Module initialization and cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) * --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static int __init dme1737_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) unsigned short addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) err = i2c_add_driver(&dme1737_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (dme1737_isa_detect(0x2e, &addr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) dme1737_isa_detect(0x4e, &addr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) (!probe_all_addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) (dme1737_isa_detect(0x162e, &addr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) dme1737_isa_detect(0x164e, &addr)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) /* Return 0 if we didn't find an ISA device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) err = platform_driver_register(&dme1737_isa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) goto exit_del_i2c_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) /* Sets global pdev as a side effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) err = dme1737_isa_device_add(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) goto exit_del_isa_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) exit_del_isa_driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) platform_driver_unregister(&dme1737_isa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) exit_del_i2c_driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) i2c_del_driver(&dme1737_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) static void __exit dme1737_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) if (pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) platform_driver_unregister(&dme1737_isa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) i2c_del_driver(&dme1737_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) MODULE_DESCRIPTION("DME1737 sensors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) module_init(dme1737_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) module_exit(dme1737_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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