^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Fan Control HDL CORE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2019 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/fpga/adi-axi-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ADI_REG_RSTN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADI_REG_PWM_WIDTH 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADI_REG_TACH_PERIOD 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADI_REG_TACH_TOLERANCE 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADI_REG_PWM_PERIOD 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADI_REG_TACH_MEASUR 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADI_REG_TEMPERATURE 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADI_REG_IRQ_MASK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADI_REG_IRQ_PENDING 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADI_REG_IRQ_SRC 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* IRQ sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADI_IRQ_SRC_PWM_CHANGED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADI_IRQ_SRC_TACH_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADI_IRQ_SRC_TEMP_INCREASE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADI_IRQ_SRC_NEW_MEASUR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADI_IRQ_SRC_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADI_IRQ_MASK_OUT_ALL 0xFFFFFFFFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SYSFS_PWM_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct axi_fan_control_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* pulses per revolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 ppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool hw_pwm_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) bool update_tacho_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 fan_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline void axi_iowrite(const u32 val, const u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct axi_fan_control_data *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) iowrite32(val, ctl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline u32 axi_ioread(const u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct axi_fan_control_data *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return ioread32(ctl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * PWM_PERIOD is a RO register set by the core. It should never be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * For now we are trusting the HW...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return DIV_ROUND_CLOSEST(pwm_width * SYSFS_PWM_MAX, pwm_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int axi_fan_control_set_pwm_duty(const long val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct axi_fan_control_data *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 new_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) long __val = clamp_val(val, 0, SYSFS_PWM_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) new_width = DIV_ROUND_CLOSEST(__val * pwm_period, SYSFS_PWM_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) axi_iowrite(new_width, ADI_REG_PWM_WIDTH, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static long axi_fan_control_get_fan_rpm(const struct axi_fan_control_data *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const u32 tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (tach == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* should we return error, EAGAIN maybe? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * The tacho period should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * TACH = 60/(ppr * rpm), where rpm is revolutions per second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * and ppr is pulses per revolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Given the tacho period, we can multiply it by the input clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * so that we know how many clocks we need to have this period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * From this, we can derive the RPM value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return DIV_ROUND_CLOSEST(60 * ctl->clk_rate, ctl->ppr * tach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int axi_fan_control_read_temp(struct device *dev, u32 attr, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) long raw_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) raw_temp = axi_ioread(ADI_REG_TEMPERATURE, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * The formula for the temperature is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * T = (ADC * 501.3743 / 2^bits) - 273.6777
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * It's multiplied by 1000 to have millidegrees as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * specified by the hwmon sysfs interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *val = ((raw_temp * 501374) >> 16) - 273677;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int axi_fan_control_read_fan(struct device *dev, u32 attr, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case hwmon_fan_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *val = ctl->fan_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* clear it now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ctl->fan_fault = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case hwmon_fan_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *val = axi_fan_control_get_fan_rpm(ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int axi_fan_control_read_pwm(struct device *dev, u32 attr, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case hwmon_pwm_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *val = axi_fan_control_get_pwm_duty(ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int axi_fan_control_write_pwm(struct device *dev, u32 attr, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case hwmon_pwm_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return axi_fan_control_set_pwm_duty(val, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int axi_fan_control_read_labels(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 attr, int channel, const char **str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case hwmon_fan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *str = "FAN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *str = "SYSMON4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int axi_fan_control_read(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case hwmon_fan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return axi_fan_control_read_fan(dev, attr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return axi_fan_control_read_pwm(dev, attr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return axi_fan_control_read_temp(dev, attr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int axi_fan_control_write(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return axi_fan_control_write_pwm(dev, attr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static umode_t axi_fan_control_fan_is_visible(const u32 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case hwmon_fan_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case hwmon_fan_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case hwmon_fan_label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static umode_t axi_fan_control_pwm_is_visible(const u32 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case hwmon_pwm_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static umode_t axi_fan_control_temp_is_visible(const u32 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case hwmon_temp_label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static umode_t axi_fan_control_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case hwmon_fan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return axi_fan_control_fan_is_visible(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case hwmon_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return axi_fan_control_pwm_is_visible(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return axi_fan_control_temp_is_visible(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * This core has two main ways of changing the PWM duty cycle. It is done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * either by a request from userspace (writing on pwm1_input) or by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * core itself. When the change is done by the core, it will use predefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * parameters to evaluate the tach signal and, on that case we cannot set them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * On the other hand, when the request is done by the user, with some arbitrary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * value that the core does not now about, we have to provide the tach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * parameters so that, the core can evaluate the signal. On the IRQ handler we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * distinguish this by using the ADI_IRQ_SRC_TEMP_INCREASE interrupt. This tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * us that the CORE requested a new duty cycle. After this, there is 5s delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * on which the core waits for the fan rotation speed to stabilize. After this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * we get ADI_IRQ_SRC_PWM_CHANGED irq where we will decide if we need to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * the tach parameters or not on the next tach measurement cycle (corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * already to the ney duty cycle) based on the %ctl->hw_pwm_req flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static irqreturn_t axi_fan_control_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct axi_fan_control_data *ctl = (struct axi_fan_control_data *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 irq_pending = axi_ioread(ADI_REG_IRQ_PENDING, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (irq_pending & ADI_IRQ_SRC_NEW_MEASUR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ctl->update_tacho_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 new_tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* get 25% tolerance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 tach_tol = DIV_ROUND_CLOSEST(new_tach * 25, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* set new tacho parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) axi_iowrite(new_tach, ADI_REG_TACH_PERIOD, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) axi_iowrite(tach_tol, ADI_REG_TACH_TOLERANCE, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ctl->update_tacho_params = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (irq_pending & ADI_IRQ_SRC_PWM_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * if the pwm changes on behalf of software,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * we need to provide new tacho parameters to the core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Wait for the next measurement for that...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!ctl->hw_pwm_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ctl->update_tacho_params = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ctl->hw_pwm_req = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sysfs_notify(&ctl->hdev->kobj, NULL, "pwm1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (irq_pending & ADI_IRQ_SRC_TEMP_INCREASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* hardware requested a new pwm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ctl->hw_pwm_req = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (irq_pending & ADI_IRQ_SRC_TACH_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctl->fan_fault = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clear_mask = irq_pending & ADI_IRQ_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) axi_iowrite(clear_mask, ADI_REG_IRQ_PENDING, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int axi_fan_control_init(struct axi_fan_control_data *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) const struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* get fan pulses per revolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = of_property_read_u32(np, "pulses-per-revolution", &ctl->ppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* 1, 2 and 4 are the typical and accepted values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ctl->ppr != 1 && ctl->ppr != 2 && ctl->ppr != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Enable all IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) axi_iowrite(ADI_IRQ_MASK_OUT_ALL &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ~(ADI_IRQ_SRC_NEW_MEASUR | ADI_IRQ_SRC_TACH_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ADI_IRQ_SRC_PWM_CHANGED | ADI_IRQ_SRC_TEMP_INCREASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ADI_REG_IRQ_MASK, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* bring the device out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) axi_iowrite(0x01, ADI_REG_RSTN, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct hwmon_channel_info *axi_fan_control_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) HWMON_CHANNEL_INFO(pwm, HWMON_PWM_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_LABEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_LABEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct hwmon_ops axi_fan_control_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .is_visible = axi_fan_control_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .read = axi_fan_control_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .write = axi_fan_control_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .read_string = axi_fan_control_read_labels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct hwmon_chip_info axi_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .ops = &axi_fan_control_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .info = axi_fan_control_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const u32 version_1_0_0 = ADI_AXI_PCORE_VER(1, 0, 'a');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct of_device_id axi_fan_control_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .compatible = "adi,axi-fan-control-1.00.a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .data = (void *)&version_1_0_0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_DEVICE_TABLE(of, axi_fan_control_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int axi_fan_control_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct axi_fan_control_data *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const char *name = "axi_fan_control";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) id = of_match_node(axi_fan_control_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ctl = devm_kzalloc(&pdev->dev, sizeof(*ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ctl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (IS_ERR(ctl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return PTR_ERR(ctl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_err(&pdev->dev, "clk_get failed with %ld\n", PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ctl->clk_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!ctl->clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) version = axi_ioread(ADI_AXI_REG_VERSION, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ADI_AXI_PCORE_VER_MAJOR(version) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(&pdev->dev, "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ADI_AXI_PCORE_VER_MINOR((*(u32 *)id->data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ADI_AXI_PCORE_VER_PATCH((*(u32 *)id->data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ADI_AXI_PCORE_VER_MAJOR(version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ADI_AXI_PCORE_VER_MINOR(version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ADI_AXI_PCORE_VER_PATCH(version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ctl->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ctl->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ctl->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = devm_request_threaded_irq(&pdev->dev, ctl->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) axi_fan_control_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pdev->driver_override, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(&pdev->dev, "failed to request an irq, %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = axi_fan_control_init(ctl, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(&pdev->dev, "Failed to initialize device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &axi_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return PTR_ERR_OR_ZERO(ctl->hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct platform_driver axi_fan_control_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "axi_fan_control_driver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .of_match_table = axi_fan_control_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .probe = axi_fan_control_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) module_platform_driver(axi_fan_control_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_DESCRIPTION("Analog Devices Fan Control HDL CORE driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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