^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Synaptics AS370 SoC Hardware Monitoring Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Synaptics Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jisheng Zhang <jszhang@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define T_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define V_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NMOS_SEL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PMOS_SEL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BN_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EOC BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct as370_hwmon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void init_pvt(struct as370_hwmon *hwmon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __iomem *addr = hwmon->base + CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) val = PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) val |= T_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) val |= EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) val &= ~PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int as370_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct as370_hwmon *hwmon = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val = readl_relaxed(hwmon->base + STS) & BN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *temp = DIV_ROUND_CLOSEST(val * 251802, 4096) - 85525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static umode_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) as370_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const u32 as370_hwmon_temp_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) HWMON_T_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct hwmon_channel_info as370_hwmon_temp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .type = hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .config = as370_hwmon_temp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct hwmon_channel_info *as370_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) &as370_hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct hwmon_ops as370_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .is_visible = as370_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .read = as370_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct hwmon_chip_info as370_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .ops = &as370_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .info = as370_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int as370_hwmon_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct as370_hwmon *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!hwmon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) hwmon->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (IS_ERR(hwmon->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return PTR_ERR(hwmon->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) init_pvt(hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hwmon_dev = devm_hwmon_device_register_with_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "as370",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) hwmon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) &as370_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct of_device_id as370_hwmon_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .compatible = "syna,as370-hwmon" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MODULE_DEVICE_TABLE(of, as370_hwmon_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct platform_driver as370_hwmon_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .probe = as370_hwmon_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "as370-hwmon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .of_match_table = as370_hwmon_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) module_platform_driver(as370_hwmon_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MODULE_AUTHOR("Jisheng Zhang<jszhang@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_DESCRIPTION("Synaptics AS370 SoC hardware monitor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags