^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adt7475 - Thermal sensor driver for the ADT7475 chip and derivatives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2008, Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Derived from the lm83 driver by Jean Delvare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/hwmon-vid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/util_macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Indexes for the sysfs hooks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CONTROL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AUTOMIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define THERM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HYSTERSIS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * These are unique identifiers for the sysfs functions - unlike the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * numbers above, these are not also indexes into an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ALARM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FAULT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 7475 Common Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_DEVREV2 0x12 /* ADT7490 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_VTT 0x1E /* ADT7490 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_EXTEND3 0x1F /* ADT7490 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_VOLTAGE_BASE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_TEMP_BASE 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_TACH_BASE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_PWM_BASE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_PWM_MAX_BASE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_DEVID 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_VENDID 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_DEVID2 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_CONFIG1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_STATUS1 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_STATUS2 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_VID 0x43 /* ADT7476 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_VOLTAGE_MIN_BASE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_VOLTAGE_MAX_BASE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_TEMP_MIN_BASE 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_TEMP_MAX_BASE 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_TACH_MIN_BASE 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_PWM_CONFIG_BASE 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_TEMP_TRANGE_BASE 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_ENHANCE_ACOUSTICS1 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_ENHANCE_ACOUSTICS2 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_PWM_MIN_BASE 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_TEMP_TMIN_BASE 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REG_TEMP_THERM_BASE 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_REMOTE1_HYSTERSIS 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_REMOTE2_HYSTERSIS 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_TEMP_OFFSET_BASE 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define REG_CONFIG2 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_EXTEND1 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_EXTEND2 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_CONFIG3 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_CONFIG5 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_CONFIG4 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_STATUS4 0x81 /* ADT7490 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_VTT_MIN 0x84 /* ADT7490 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_VTT_MAX 0x86 /* ADT7490 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VID_VIDSEL 0x80 /* ADT7476 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CONFIG2_ATTN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CONFIG3_SMBALERT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CONFIG3_THERM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CONFIG4_PINFUNC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CONFIG4_MAXDUTY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CONFIG4_ATTN_IN10 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CONFIG4_ATTN_IN43 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CONFIG5_TWOSCOMP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CONFIG5_TEMPOFFSET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* ADT7475 Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ADT7475_TEMP_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ADT7475_TACH_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ADT7475_PWM_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Macro to read the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define adt7475_read(reg) i2c_smbus_read_byte_data(client, (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Macros to easily index the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PWM_REG(idx) (REG_PWM_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEMP_REG(idx) (REG_TEMP_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum chips { adt7473, adt7475, adt7476, adt7490 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct i2c_device_id adt7475_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { "adt7473", adt7473 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { "adt7475", adt7475 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { "adt7476", adt7476 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { "adt7490", adt7490 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_DEVICE_TABLE(i2c, adt7475_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct of_device_id __maybe_unused adt7475_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .compatible = "adi,adt7473",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .data = (void *)adt7473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .compatible = "adi,adt7475",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .data = (void *)adt7475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .compatible = "adi,adt7476",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .data = (void *)adt7476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .compatible = "adi,adt7490",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .data = (void *)adt7490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DEVICE_TABLE(of, adt7475_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct adt7475_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long measure_updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 config4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 config5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 has_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 bypass_attn; /* Bypass voltage attenuator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 has_pwm2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 has_fan4:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 has_vid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 voltage[3][6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 temp[7][3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 tach[2][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 pwm[4][3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 range[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 pwmctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 pwmchan[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 enh_acoustics[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 vrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct attribute_group *groups[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct i2c_driver adt7475_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct adt7475_data *adt7475_update_device(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void adt7475_read_hystersis(struct i2c_client *client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void adt7475_read_pwm(struct i2c_client *client, int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Given a temp value, convert it to register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline u16 temp2reg(struct adt7475_data *data, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!(data->config5 & CONFIG5_TWOSCOMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val = clamp_val(val, -64000, 191000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = (val + 64500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) val = clamp_val(val, -128000, 127000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (val < -500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = (256500 + val) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = (val + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Given a register value, convert it to a real temp value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline int reg2temp(struct adt7475_data *data, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (data->config5 & CONFIG5_TWOSCOMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (reg >= 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return (reg - 1024) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return reg * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return (reg - 256) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline int tach2rpm(u16 tach)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (tach == 0 || tach == 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return (90000 * 60) / tach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline u16 rpm2tach(unsigned long rpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (rpm == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return clamp_val((90000 * 60) / rpm, 1, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Scaling factors for voltage inputs, taken from the ADT7490 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const int adt7473_in_scaling[ADT7475_VOLTAGE_COUNT + 1][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 45, 94 }, /* +2.5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 175, 525 }, /* Vccp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 68, 71 }, /* Vcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 93, 47 }, /* +5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 120, 20 }, /* +12V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 45, 45 }, /* Vtt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline int reg2volt(int channel, u16 reg, u8 bypass_attn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const int *r = adt7473_in_scaling[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (bypass_attn & (1 << channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return DIV_ROUND_CLOSEST(reg * 2250, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return DIV_ROUND_CLOSEST(reg * (r[0] + r[1]) * 2250, r[1] * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static inline u16 volt2reg(int channel, long volt, u8 bypass_attn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) const int *r = adt7473_in_scaling[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (bypass_attn & (1 << channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg = DIV_ROUND_CLOSEST(volt * 1024, 2250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) reg = DIV_ROUND_CLOSEST(volt * r[1] * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (r[0] + r[1]) * 2250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return clamp_val(reg, 0, 1023) & (0xff << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int adt7475_read_word(struct i2c_client *client, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) val1 = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (val1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val2 = i2c_smbus_read_byte_data(client, reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (val2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return val1 | (val2 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void adt7475_write_word(struct i2c_client *client, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i2c_smbus_write_byte_data(client, reg + 1, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) i2c_smbus_write_byte_data(client, reg, val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static ssize_t voltage_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) switch (sattr->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return sprintf(buf, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (data->alarms >> sattr->index) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val = data->voltage[sattr->nr][sattr->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return sprintf(buf, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) reg2volt(sattr->index, val, data->bypass_attn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static ssize_t voltage_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) data->voltage[sattr->nr][sattr->index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) volt2reg(sattr->index, val, data->bypass_attn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (sattr->index < ADT7475_VOLTAGE_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (sattr->nr == MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg = VOLTAGE_MIN_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reg = VOLTAGE_MAX_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (sattr->nr == MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg = REG_VTT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) reg = REG_VTT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) i2c_smbus_write_byte_data(client, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) data->voltage[sattr->nr][sattr->index] >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static ssize_t temp_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (sattr->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case HYSTERSIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) out = data->temp[sattr->nr][sattr->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (sattr->index != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) out = (out >> 4) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) out = (out & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * Show the value as an absolute number tied to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * THERM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) out = reg2temp(data, data->temp[THERM][sattr->index]) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) out * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Offset is always 2's complement, regardless of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * setting in CONFIG5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) out = (s8)data->temp[sattr->nr][sattr->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (data->config5 & CONFIG5_TEMPOFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) out *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) out *= 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) out = (data->alarms >> (sattr->index + 4)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case FAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Note - only for remote1 and remote2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) out = !!(data->alarms & (sattr->index ? 0x8000 : 0x4000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* All other temp values are in the configured format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) out = reg2temp(data, data->temp[sattr->nr][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return sprintf(buf, "%d\n", out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static ssize_t temp_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned char reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* We need the config register in all cases for temp <-> reg conv. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) data->config5 = adt7475_read(REG_CONFIG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) switch (sattr->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (data->config5 & CONFIG5_TEMPOFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val = clamp_val(val, -63000, 127000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) out = data->temp[OFFSET][sattr->index] = val / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val = clamp_val(val, -63000, 64000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) out = data->temp[OFFSET][sattr->index] = val / 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case HYSTERSIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * The value will be given as an absolute value, turn it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * into an offset based on THERM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Read fresh THERM and HYSTERSIS values from the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) data->temp[THERM][sattr->index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) adt7475_read(TEMP_THERM_REG(sattr->index)) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) adt7475_read_hystersis(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) temp = reg2temp(data, data->temp[THERM][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) val = clamp_val(val, temp - 15000, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) val = (temp - val) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (sattr->index != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) data->temp[HYSTERSIS][sattr->index] &= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) data->temp[HYSTERSIS][sattr->index] |= (val & 0xF) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) data->temp[HYSTERSIS][sattr->index] &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) data->temp[HYSTERSIS][sattr->index] |= (val & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) out = data->temp[HYSTERSIS][sattr->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) data->temp[sattr->nr][sattr->index] = temp2reg(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * We maintain an extra 2 digits of precision for simplicity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * - shift those back off before writing the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) out = (u8) (data->temp[sattr->nr][sattr->index] >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) switch (sattr->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) reg = TEMP_MIN_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) reg = TEMP_MAX_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) reg = TEMP_OFFSET_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case AUTOMIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) reg = TEMP_TMIN_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case THERM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) reg = TEMP_THERM_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case HYSTERSIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (sattr->index != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) reg = REG_REMOTE1_HYSTERSIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) reg = REG_REMOTE2_HYSTERSIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) i2c_smbus_write_byte_data(client, reg, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Assuming CONFIG6[SLOW] is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const int ad7475_st_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 37500, 18800, 12500, 7500, 4700, 3100, 1600, 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static ssize_t temp_st_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (sattr->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val = data->enh_acoustics[0] & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val = (data->enh_acoustics[1] >> 4) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val = data->enh_acoustics[1] & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (val & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return sprintf(buf, "%d\n", ad7475_st_map[val & 0x7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return sprintf(buf, "0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static ssize_t temp_st_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int shift, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ulong val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (kstrtoul(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) switch (sattr->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) reg = REG_ENHANCE_ACOUSTICS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) reg = REG_ENHANCE_ACOUSTICS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) reg = REG_ENHANCE_ACOUSTICS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) shift = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (val > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) val = find_closest_descending(val, ad7475_st_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ARRAY_SIZE(ad7475_st_map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) val |= 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) data->enh_acoustics[idx] &= ~(0xf << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) data->enh_acoustics[idx] |= (val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) i2c_smbus_write_byte_data(client, reg, data->enh_acoustics[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Table of autorange values - the user will write the value in millidegrees,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * and we'll convert it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const int autorange_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 2000, 2500, 3330, 4000, 5000, 6670, 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 10000, 13330, 16000, 20000, 26670, 32000, 40000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 53330, 80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static ssize_t point2_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int out, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) out = (data->range[sattr->index] >> 4) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val = reg2temp(data, data->temp[AUTOMIN][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return sprintf(buf, "%d\n", val + autorange_table[out]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static ssize_t point2_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Get a fresh copy of the needed registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) data->config5 = adt7475_read(REG_CONFIG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) data->temp[AUTOMIN][sattr->index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) adt7475_read(TEMP_TMIN_REG(sattr->index)) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) data->range[sattr->index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) adt7475_read(TEMP_TRANGE_REG(sattr->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * The user will write an absolute value, so subtract the start point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * to figure the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) temp = reg2temp(data, data->temp[AUTOMIN][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val = clamp_val(val, temp + autorange_table[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) temp + autorange_table[ARRAY_SIZE(autorange_table) - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) val -= temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Find the nearest table entry to what the user wrote */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) val = find_closest(val, autorange_table, ARRAY_SIZE(autorange_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) data->range[sattr->index] &= ~0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) data->range[sattr->index] |= val << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) i2c_smbus_write_byte_data(client, TEMP_TRANGE_REG(sattr->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) data->range[sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static ssize_t tach_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (sattr->nr == ALARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) out = (data->alarms >> (sattr->index + 10)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) out = tach2rpm(data->tach[sattr->nr][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return sprintf(buf, "%d\n", out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static ssize_t tach_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (kstrtoul(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) data->tach[MIN][sattr->index] = rpm2tach(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) adt7475_write_word(client, TACH_MIN_REG(sattr->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) data->tach[MIN][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static ssize_t pwm_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return sprintf(buf, "%d\n", data->pwm[sattr->nr][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static ssize_t pwmchan_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return sprintf(buf, "%d\n", data->pwmchan[sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static ssize_t pwmctrl_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return sprintf(buf, "%d\n", data->pwmctl[sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static ssize_t pwm_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned char reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) switch (sattr->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Get a fresh value for CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) data->pwm[CONTROL][sattr->index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) adt7475_read(PWM_CONFIG_REG(sattr->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * If we are not in manual mode, then we shouldn't allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * the user to set the pwm speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (((data->pwm[CONTROL][sattr->index] >> 5) & 7) != 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) reg = PWM_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) reg = PWM_MIN_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) reg = PWM_MAX_REG(sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) data->pwm[sattr->nr][sattr->index] = clamp_val(val, 0, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) i2c_smbus_write_byte_data(client, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) data->pwm[sattr->nr][sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static ssize_t stall_disable_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 mask = BIT(5 + sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return sprintf(buf, "%d\n", !!(data->enh_acoustics[0] & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static ssize_t stall_disable_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 mask = BIT(5 + sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) data->enh_acoustics[0] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) data->enh_acoustics[0] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) i2c_smbus_write_byte_data(client, REG_ENHANCE_ACOUSTICS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) data->enh_acoustics[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* Called by set_pwmctrl and set_pwmchan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int hw_set_pwm(struct i2c_client *client, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unsigned int pwmctl, unsigned int pwmchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct adt7475_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) switch (pwmctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) val = 0x03; /* Run at full speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) val = 0x07; /* Manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) switch (pwmchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Remote1 controls PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* local controls PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) val = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* remote2 controls PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) val = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* local/remote2 control PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) val = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* All three control PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) val = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) data->pwmctl[index] = pwmctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) data->pwmchan[index] = pwmchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) data->pwm[CONTROL][index] &= ~0xE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) data->pwm[CONTROL][index] |= (val & 7) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) i2c_smbus_write_byte_data(client, PWM_CONFIG_REG(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) data->pwm[CONTROL][index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static ssize_t pwmchan_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Read Modify Write PWM values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) adt7475_read_pwm(client, sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) r = hw_set_pwm(client, sattr->index, data->pwmctl[sattr->index], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) count = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static ssize_t pwmctrl_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Read Modify Write PWM values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) adt7475_read_pwm(client, sattr->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) r = hw_set_pwm(client, sattr->index, val, data->pwmchan[sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) count = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* List of frequencies for the PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const int pwmfreq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) 11, 14, 22, 29, 35, 44, 58, 88, 22500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static ssize_t pwmfreq_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) idx = clamp_val(data->range[sattr->index] & 0xf, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ARRAY_SIZE(pwmfreq_table) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return sprintf(buf, "%d\n", pwmfreq_table[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static ssize_t pwmfreq_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) out = find_closest(val, pwmfreq_table, ARRAY_SIZE(pwmfreq_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) data->range[sattr->index] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) adt7475_read(TEMP_TRANGE_REG(sattr->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) data->range[sattr->index] &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) data->range[sattr->index] |= out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) i2c_smbus_write_byte_data(client, TEMP_TRANGE_REG(sattr->index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) data->range[sattr->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static ssize_t pwm_use_point2_pwm_at_crit_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return sprintf(buf, "%d\n", !!(data->config4 & CONFIG4_MAXDUTY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static ssize_t pwm_use_point2_pwm_at_crit_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (val != 0 && val != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) data->config4 = i2c_smbus_read_byte_data(client, REG_CONFIG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) data->config4 |= CONFIG4_MAXDUTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) data->config4 &= ~CONFIG4_MAXDUTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) i2c_smbus_write_byte_data(client, REG_CONFIG4, data->config4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static ssize_t vrm_show(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return sprintf(buf, "%d\n", (int)data->vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static ssize_t vrm_store(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (kstrtol(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (val < 0 || val > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) data->vrm = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static ssize_t cpu0_vid_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct device_attribute *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct adt7475_data *data = adt7475_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static SENSOR_DEVICE_ATTR_2_RO(in0_input, voltage, INPUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static SENSOR_DEVICE_ATTR_2_RW(in0_max, voltage, MAX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static SENSOR_DEVICE_ATTR_2_RW(in0_min, voltage, MIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static SENSOR_DEVICE_ATTR_2_RO(in0_alarm, voltage, ALARM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static SENSOR_DEVICE_ATTR_2_RO(in1_input, voltage, INPUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static SENSOR_DEVICE_ATTR_2_RW(in1_max, voltage, MAX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static SENSOR_DEVICE_ATTR_2_RW(in1_min, voltage, MIN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static SENSOR_DEVICE_ATTR_2_RO(in1_alarm, voltage, ALARM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static SENSOR_DEVICE_ATTR_2_RO(in2_input, voltage, INPUT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static SENSOR_DEVICE_ATTR_2_RW(in2_max, voltage, MAX, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static SENSOR_DEVICE_ATTR_2_RW(in2_min, voltage, MIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static SENSOR_DEVICE_ATTR_2_RO(in2_alarm, voltage, ALARM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static SENSOR_DEVICE_ATTR_2_RO(in3_input, voltage, INPUT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static SENSOR_DEVICE_ATTR_2_RW(in3_max, voltage, MAX, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static SENSOR_DEVICE_ATTR_2_RW(in3_min, voltage, MIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static SENSOR_DEVICE_ATTR_2_RO(in3_alarm, voltage, ALARM, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static SENSOR_DEVICE_ATTR_2_RO(in4_input, voltage, INPUT, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static SENSOR_DEVICE_ATTR_2_RW(in4_max, voltage, MAX, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static SENSOR_DEVICE_ATTR_2_RW(in4_min, voltage, MIN, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static SENSOR_DEVICE_ATTR_2_RO(in4_alarm, voltage, ALARM, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static SENSOR_DEVICE_ATTR_2_RO(in5_input, voltage, INPUT, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static SENSOR_DEVICE_ATTR_2_RW(in5_max, voltage, MAX, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static SENSOR_DEVICE_ATTR_2_RW(in5_min, voltage, MIN, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static SENSOR_DEVICE_ATTR_2_RO(in5_alarm, voltage, ALARM, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static SENSOR_DEVICE_ATTR_2_RO(temp1_input, temp, INPUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static SENSOR_DEVICE_ATTR_2_RO(temp1_alarm, temp, ALARM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static SENSOR_DEVICE_ATTR_2_RO(temp1_fault, temp, FAULT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static SENSOR_DEVICE_ATTR_2_RW(temp1_max, temp, MAX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static SENSOR_DEVICE_ATTR_2_RW(temp1_min, temp, MIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static SENSOR_DEVICE_ATTR_2_RW(temp1_offset, temp, OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static SENSOR_DEVICE_ATTR_2_RW(temp1_auto_point1_temp, temp, AUTOMIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static SENSOR_DEVICE_ATTR_2_RW(temp1_auto_point2_temp, point2, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static SENSOR_DEVICE_ATTR_2_RW(temp1_crit, temp, THERM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static SENSOR_DEVICE_ATTR_2_RW(temp1_crit_hyst, temp, HYSTERSIS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static SENSOR_DEVICE_ATTR_2_RW(temp1_smoothing, temp_st, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static SENSOR_DEVICE_ATTR_2_RO(temp2_input, temp, INPUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static SENSOR_DEVICE_ATTR_2_RO(temp2_alarm, temp, ALARM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static SENSOR_DEVICE_ATTR_2_RW(temp2_max, temp, MAX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static SENSOR_DEVICE_ATTR_2_RW(temp2_min, temp, MIN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static SENSOR_DEVICE_ATTR_2_RW(temp2_offset, temp, OFFSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static SENSOR_DEVICE_ATTR_2_RW(temp2_auto_point1_temp, temp, AUTOMIN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static SENSOR_DEVICE_ATTR_2_RW(temp2_auto_point2_temp, point2, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static SENSOR_DEVICE_ATTR_2_RW(temp2_crit, temp, THERM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static SENSOR_DEVICE_ATTR_2_RW(temp2_crit_hyst, temp, HYSTERSIS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static SENSOR_DEVICE_ATTR_2_RW(temp2_smoothing, temp_st, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static SENSOR_DEVICE_ATTR_2_RO(temp3_input, temp, INPUT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static SENSOR_DEVICE_ATTR_2_RO(temp3_alarm, temp, ALARM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static SENSOR_DEVICE_ATTR_2_RO(temp3_fault, temp, FAULT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static SENSOR_DEVICE_ATTR_2_RW(temp3_max, temp, MAX, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static SENSOR_DEVICE_ATTR_2_RW(temp3_min, temp, MIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static SENSOR_DEVICE_ATTR_2_RW(temp3_offset, temp, OFFSET, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static SENSOR_DEVICE_ATTR_2_RW(temp3_auto_point1_temp, temp, AUTOMIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static SENSOR_DEVICE_ATTR_2_RW(temp3_auto_point2_temp, point2, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static SENSOR_DEVICE_ATTR_2_RW(temp3_crit, temp, THERM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static SENSOR_DEVICE_ATTR_2_RW(temp3_crit_hyst, temp, HYSTERSIS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static SENSOR_DEVICE_ATTR_2_RW(temp3_smoothing, temp_st, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static SENSOR_DEVICE_ATTR_2_RO(fan1_input, tach, INPUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static SENSOR_DEVICE_ATTR_2_RW(fan1_min, tach, MIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static SENSOR_DEVICE_ATTR_2_RO(fan1_alarm, tach, ALARM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static SENSOR_DEVICE_ATTR_2_RO(fan2_input, tach, INPUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static SENSOR_DEVICE_ATTR_2_RW(fan2_min, tach, MIN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static SENSOR_DEVICE_ATTR_2_RO(fan2_alarm, tach, ALARM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static SENSOR_DEVICE_ATTR_2_RO(fan3_input, tach, INPUT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static SENSOR_DEVICE_ATTR_2_RW(fan3_min, tach, MIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static SENSOR_DEVICE_ATTR_2_RO(fan3_alarm, tach, ALARM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static SENSOR_DEVICE_ATTR_2_RO(fan4_input, tach, INPUT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static SENSOR_DEVICE_ATTR_2_RW(fan4_min, tach, MIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static SENSOR_DEVICE_ATTR_2_RO(fan4_alarm, tach, ALARM, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static SENSOR_DEVICE_ATTR_2_RW(pwm1, pwm, INPUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static SENSOR_DEVICE_ATTR_2_RW(pwm1_freq, pwmfreq, INPUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static SENSOR_DEVICE_ATTR_2_RW(pwm1_enable, pwmctrl, INPUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static SENSOR_DEVICE_ATTR_2_RW(pwm1_auto_channels_temp, pwmchan, INPUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static SENSOR_DEVICE_ATTR_2_RW(pwm1_auto_point1_pwm, pwm, MIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static SENSOR_DEVICE_ATTR_2_RW(pwm1_auto_point2_pwm, pwm, MAX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static SENSOR_DEVICE_ATTR_2_RW(pwm1_stall_disable, stall_disable, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static SENSOR_DEVICE_ATTR_2_RW(pwm2, pwm, INPUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static SENSOR_DEVICE_ATTR_2_RW(pwm2_freq, pwmfreq, INPUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static SENSOR_DEVICE_ATTR_2_RW(pwm2_enable, pwmctrl, INPUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static SENSOR_DEVICE_ATTR_2_RW(pwm2_auto_channels_temp, pwmchan, INPUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static SENSOR_DEVICE_ATTR_2_RW(pwm2_auto_point1_pwm, pwm, MIN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static SENSOR_DEVICE_ATTR_2_RW(pwm2_auto_point2_pwm, pwm, MAX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static SENSOR_DEVICE_ATTR_2_RW(pwm2_stall_disable, stall_disable, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static SENSOR_DEVICE_ATTR_2_RW(pwm3, pwm, INPUT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static SENSOR_DEVICE_ATTR_2_RW(pwm3_freq, pwmfreq, INPUT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static SENSOR_DEVICE_ATTR_2_RW(pwm3_enable, pwmctrl, INPUT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static SENSOR_DEVICE_ATTR_2_RW(pwm3_auto_channels_temp, pwmchan, INPUT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static SENSOR_DEVICE_ATTR_2_RW(pwm3_auto_point1_pwm, pwm, MIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static SENSOR_DEVICE_ATTR_2_RW(pwm3_auto_point2_pwm, pwm, MAX, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static SENSOR_DEVICE_ATTR_2_RW(pwm3_stall_disable, stall_disable, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Non-standard name, might need revisiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static DEVICE_ATTR_RW(pwm_use_point2_pwm_at_crit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static DEVICE_ATTR_RW(vrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static DEVICE_ATTR_RO(cpu0_vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static struct attribute *adt7475_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) &sensor_dev_attr_in1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) &sensor_dev_attr_in1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) &sensor_dev_attr_in1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) &sensor_dev_attr_in1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) &sensor_dev_attr_in2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) &sensor_dev_attr_in2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) &sensor_dev_attr_in2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) &sensor_dev_attr_in2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) &sensor_dev_attr_temp1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) &sensor_dev_attr_temp1_fault.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) &sensor_dev_attr_temp1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) &sensor_dev_attr_temp1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) &sensor_dev_attr_temp1_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) &sensor_dev_attr_temp1_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) &sensor_dev_attr_temp1_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) &sensor_dev_attr_temp1_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) &sensor_dev_attr_temp1_smoothing.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) &sensor_dev_attr_temp2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) &sensor_dev_attr_temp2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) &sensor_dev_attr_temp2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) &sensor_dev_attr_temp2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) &sensor_dev_attr_temp2_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) &sensor_dev_attr_temp2_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) &sensor_dev_attr_temp2_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) &sensor_dev_attr_temp2_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) &sensor_dev_attr_temp2_smoothing.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) &sensor_dev_attr_temp3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) &sensor_dev_attr_temp3_fault.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) &sensor_dev_attr_temp3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) &sensor_dev_attr_temp3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) &sensor_dev_attr_temp3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) &sensor_dev_attr_temp3_offset.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) &sensor_dev_attr_temp3_auto_point1_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) &sensor_dev_attr_temp3_auto_point2_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) &sensor_dev_attr_temp3_crit.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) &sensor_dev_attr_temp3_smoothing.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) &sensor_dev_attr_fan1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) &sensor_dev_attr_fan1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) &sensor_dev_attr_fan1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) &sensor_dev_attr_fan2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) &sensor_dev_attr_fan2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) &sensor_dev_attr_fan2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) &sensor_dev_attr_fan3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) &sensor_dev_attr_fan3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) &sensor_dev_attr_fan3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) &sensor_dev_attr_pwm1.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) &sensor_dev_attr_pwm1_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) &sensor_dev_attr_pwm1_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) &sensor_dev_attr_pwm1_stall_disable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) &sensor_dev_attr_pwm3.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) &sensor_dev_attr_pwm3_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) &sensor_dev_attr_pwm3_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) &sensor_dev_attr_pwm3_stall_disable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) &dev_attr_pwm_use_point2_pwm_at_crit.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static struct attribute *fan4_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) &sensor_dev_attr_fan4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) &sensor_dev_attr_fan4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) &sensor_dev_attr_fan4_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static struct attribute *pwm2_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) &sensor_dev_attr_pwm2.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) &sensor_dev_attr_pwm2_freq.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) &sensor_dev_attr_pwm2_enable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) &sensor_dev_attr_pwm2_stall_disable.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static struct attribute *in0_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) &sensor_dev_attr_in0_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) &sensor_dev_attr_in0_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) &sensor_dev_attr_in0_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) &sensor_dev_attr_in0_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static struct attribute *in3_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) &sensor_dev_attr_in3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &sensor_dev_attr_in3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) &sensor_dev_attr_in3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &sensor_dev_attr_in3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static struct attribute *in4_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) &sensor_dev_attr_in4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) &sensor_dev_attr_in4_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) &sensor_dev_attr_in4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) &sensor_dev_attr_in4_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static struct attribute *in5_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) &sensor_dev_attr_in5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) &sensor_dev_attr_in5_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) &sensor_dev_attr_in5_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &sensor_dev_attr_in5_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static struct attribute *vid_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) &dev_attr_cpu0_vid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) &dev_attr_vrm.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static const struct attribute_group adt7475_attr_group = { .attrs = adt7475_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const struct attribute_group fan4_attr_group = { .attrs = fan4_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static const struct attribute_group pwm2_attr_group = { .attrs = pwm2_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const struct attribute_group in0_attr_group = { .attrs = in0_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static const struct attribute_group in3_attr_group = { .attrs = in3_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const struct attribute_group in4_attr_group = { .attrs = in4_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static const struct attribute_group in5_attr_group = { .attrs = in5_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const struct attribute_group vid_attr_group = { .attrs = vid_attrs };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int adt7475_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int vendid, devid, devid2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) vendid = adt7475_read(REG_VENDID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) devid2 = adt7475_read(REG_DEVID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (vendid != 0x41 || /* Analog Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) (devid2 & 0xf8) != 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) devid = adt7475_read(REG_DEVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (devid == 0x73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) name = "adt7473";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) else if (devid == 0x75 && client->addr == 0x2e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) name = "adt7475";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) else if (devid == 0x76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) name = "adt7476";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) else if ((devid2 & 0xfc) == 0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) name = "adt7490";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dev_dbg(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) "Couldn't detect an ADT7473/75/76/90 part at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) "0x%02x\n", (unsigned int)client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) strlcpy(info->type, name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int adt7475_update_limits(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct adt7475_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = adt7475_read(REG_CONFIG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) data->config4 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = adt7475_read(REG_CONFIG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) data->config5 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) for (i = 0; i < ADT7475_VOLTAGE_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (!(data->has_voltage & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Adjust values so they match the input precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ret = adt7475_read(VOLTAGE_MIN_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) data->voltage[MIN][i] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret = adt7475_read(VOLTAGE_MAX_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) data->voltage[MAX][i] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (data->has_voltage & (1 << 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = adt7475_read(REG_VTT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) data->voltage[MIN][5] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = adt7475_read(REG_VTT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) data->voltage[MAX][5] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) for (i = 0; i < ADT7475_TEMP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* Adjust values so they match the input precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret = adt7475_read(TEMP_MIN_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) data->temp[MIN][i] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ret = adt7475_read(TEMP_MAX_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) data->temp[MAX][i] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ret = adt7475_read(TEMP_TMIN_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) data->temp[AUTOMIN][i] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ret = adt7475_read(TEMP_THERM_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) data->temp[THERM][i] = ret << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = adt7475_read(TEMP_OFFSET_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) data->temp[OFFSET][i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) adt7475_read_hystersis(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) for (i = 0; i < ADT7475_TACH_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (i == 3 && !data->has_fan4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ret = adt7475_read_word(client, TACH_MIN_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) data->tach[MIN][i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) for (i = 0; i < ADT7475_PWM_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (i == 1 && !data->has_pwm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret = adt7475_read(PWM_MAX_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) data->pwm[MAX][i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = adt7475_read(PWM_MIN_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) data->pwm[MIN][i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Set the channel and control information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) adt7475_read_pwm(client, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ret = adt7475_read(TEMP_TRANGE_REG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) data->range[0] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ret = adt7475_read(TEMP_TRANGE_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) data->range[1] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ret = adt7475_read(TEMP_TRANGE_REG(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) data->range[2] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static int set_property_bit(const struct i2c_client *client, char *property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u8 *config, u8 bit_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) u32 prop_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int ret = of_property_read_u32(client->dev.of_node, property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) &prop_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (prop_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) *config |= (1 << bit_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) *config &= ~(1 << bit_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static int load_attenuators(const struct i2c_client *client, int chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct adt7475_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (chip == adt7476 || chip == adt7490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) set_property_bit(client, "adi,bypass-attenuator-in0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) &data->config4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) set_property_bit(client, "adi,bypass-attenuator-in1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &data->config4, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) set_property_bit(client, "adi,bypass-attenuator-in3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) &data->config4, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) set_property_bit(client, "adi,bypass-attenuator-in4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) &data->config4, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ret = i2c_smbus_write_byte_data(client, REG_CONFIG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) data->config4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) } else if (chip == adt7473 || chip == adt7475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) set_property_bit(client, "adi,bypass-attenuator-in1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) &data->config2, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ret = i2c_smbus_write_byte_data(client, REG_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) data->config2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static int adt7475_set_pwm_polarity(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) u32 states[ADT7475_PWM_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ret = of_property_read_u32_array(client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) "adi,pwm-active-state", states,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ARRAY_SIZE(states));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) for (i = 0; i < ADT7475_PWM_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ret = adt7475_read(PWM_CONFIG_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (states[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) val &= ~BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) val |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) ret = i2c_smbus_write_byte_data(client, PWM_CONFIG_REG(i), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int adt7475_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) enum chips chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static const char * const names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) [adt7473] = "ADT7473",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) [adt7475] = "ADT7475",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) [adt7476] = "ADT7476",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) [adt7490] = "ADT7490",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct adt7475_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) int i, ret = 0, revision, group_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) u8 config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) const struct i2c_device_id *id = i2c_match_id(adt7475_id, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (data == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) chip = (enum chips)of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) chip = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* Initialize device-specific values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) case adt7476:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) data->has_voltage = 0x0e; /* in1 to in3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) revision = adt7475_read(REG_DEVID2) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) case adt7490:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) data->has_voltage = 0x3e; /* in1 to in5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) revision = adt7475_read(REG_DEVID2) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (revision == 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) revision += adt7475_read(REG_DEVREV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) data->has_voltage = 0x06; /* in1, in2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) revision = adt7475_read(REG_DEVID2) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) config3 = adt7475_read(REG_CONFIG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Pin PWM2 may alternatively be used for ALERT output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (!(config3 & CONFIG3_SMBALERT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) data->has_pwm2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* Meaning of this bit is inverted for the ADT7473-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (id->driver_data == adt7473 && revision >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) data->has_pwm2 = !data->has_pwm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) data->config4 = adt7475_read(REG_CONFIG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Pin TACH4 may alternatively be used for THERM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if ((data->config4 & CONFIG4_PINFUNC) == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) data->has_fan4 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * THERM configuration is more complex on the ADT7476 and ADT7490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * because 2 different pins (TACH4 and +2.5 Vin) can be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (id->driver_data == adt7490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if ((data->config4 & CONFIG4_PINFUNC) == 0x1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) !(config3 & CONFIG3_THERM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) data->has_fan4 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (id->driver_data == adt7476 || id->driver_data == adt7490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (!(config3 & CONFIG3_THERM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) (data->config4 & CONFIG4_PINFUNC) == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) data->has_voltage |= (1 << 0); /* in0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * On the ADT7476, the +12V input pin may instead be used as VID5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * and VID pins may alternatively be used as GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (id->driver_data == adt7476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) u8 vid = adt7475_read(REG_VID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (!(vid & VID_VIDSEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) data->has_voltage |= (1 << 4); /* in4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) data->has_vid = !(adt7475_read(REG_CONFIG5) & CONFIG5_VIDGPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* Voltage attenuators can be bypassed, globally or individually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) data->config2 = adt7475_read(REG_CONFIG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ret = load_attenuators(client, chip, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) dev_warn(&client->dev, "Error configuring attenuator bypass\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (data->config2 & CONFIG2_ATTN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) data->bypass_attn = (0x3 << 3) | 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) data->bypass_attn = ((data->config4 & CONFIG4_ATTN_IN10) >> 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ((data->config4 & CONFIG4_ATTN_IN43) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) data->bypass_attn &= data->has_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * Call adt7475_read_pwm for all pwm's as this will reprogram any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * pwm's which are disabled to manual mode with 0% duty cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) for (i = 0; i < ADT7475_PWM_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) adt7475_read_pwm(client, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ret = adt7475_set_pwm_polarity(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (ret && ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) dev_warn(&client->dev, "Error configuring pwm polarity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* Start monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) case adt7475:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) case adt7476:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) i2c_smbus_write_byte_data(client, REG_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) adt7475_read(REG_CONFIG1) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) data->groups[group_num++] = &adt7475_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* Features that can be disabled individually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (data->has_fan4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) data->groups[group_num++] = &fan4_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (data->has_pwm2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) data->groups[group_num++] = &pwm2_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (data->has_voltage & (1 << 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) data->groups[group_num++] = &in0_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (data->has_voltage & (1 << 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) data->groups[group_num++] = &in3_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (data->has_voltage & (1 << 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) data->groups[group_num++] = &in4_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (data->has_voltage & (1 << 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) data->groups[group_num++] = &in5_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (data->has_vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) data->vrm = vid_which_vrm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) data->groups[group_num] = &vid_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* register device with all the acquired attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hwmon_dev = devm_hwmon_device_register_with_groups(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) client->name, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) data->groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) dev_info(&client->dev, "%s device, revision %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) names[id->driver_data], revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if ((data->has_voltage & 0x11) || data->has_fan4 || data->has_pwm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) dev_info(&client->dev, "Optional features:%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) (data->has_voltage & (1 << 0)) ? " in0" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) (data->has_voltage & (1 << 4)) ? " in4" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) data->has_fan4 ? " fan4" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) data->has_pwm2 ? " pwm2" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) data->has_vid ? " vid" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (data->bypass_attn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) dev_info(&client->dev, "Bypassing attenuators on:%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) (data->bypass_attn & (1 << 0)) ? " in0" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) (data->bypass_attn & (1 << 1)) ? " in1" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) (data->bypass_attn & (1 << 3)) ? " in3" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) (data->bypass_attn & (1 << 4)) ? " in4" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* Limits and settings, should never change update more than once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ret = adt7475_update_limits(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static struct i2c_driver adt7475_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .name = "adt7475",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .of_match_table = of_match_ptr(adt7475_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .probe_new = adt7475_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .id_table = adt7475_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .detect = adt7475_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static void adt7475_read_hystersis(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct adt7475_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) data->temp[HYSTERSIS][0] = (u16) adt7475_read(REG_REMOTE1_HYSTERSIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) data->temp[HYSTERSIS][1] = data->temp[HYSTERSIS][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) data->temp[HYSTERSIS][2] = (u16) adt7475_read(REG_REMOTE2_HYSTERSIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static void adt7475_read_pwm(struct i2c_client *client, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct adt7475_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) data->pwm[CONTROL][index] = adt7475_read(PWM_CONFIG_REG(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * Figure out the internal value for pwmctrl and pwmchan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * based on the current settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) v = (data->pwm[CONTROL][index] >> 5) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (v == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) data->pwmctl[index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) else if (v == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) data->pwmctl[index] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) else if (v == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * The fan is disabled - we don't want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * support that, so change to manual mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * set the duty cycle to 0 instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) data->pwm[INPUT][index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) data->pwm[CONTROL][index] &= ~0xE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) data->pwm[CONTROL][index] |= (7 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) i2c_smbus_write_byte_data(client, PWM_CONFIG_REG(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) data->pwm[INPUT][index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) i2c_smbus_write_byte_data(client, PWM_CONFIG_REG(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) data->pwm[CONTROL][index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) data->pwmctl[index] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) data->pwmctl[index] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) switch (v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) data->pwmchan[index] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) data->pwmchan[index] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) data->pwmchan[index] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) data->pwmchan[index] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) data->pwmchan[index] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static int adt7475_update_measure(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) u16 ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ret = adt7475_read(REG_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) data->alarms = ret << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ret = adt7475_read(REG_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) data->alarms |= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ret = adt7475_read(REG_EXTEND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ext = (ret << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ret = adt7475_read(REG_EXTEND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ext |= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) for (i = 0; i < ADT7475_VOLTAGE_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (!(data->has_voltage & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) ret = adt7475_read(VOLTAGE_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) data->voltage[INPUT][i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) (ret << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ((ext >> (i * 2)) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) for (i = 0; i < ADT7475_TEMP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret = adt7475_read(TEMP_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) data->temp[INPUT][i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) (ret << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ((ext >> ((i + 5) * 2)) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (data->has_voltage & (1 << 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ret = adt7475_read(REG_STATUS4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) data->alarms |= ret << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) ret = adt7475_read(REG_EXTEND3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ext = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ret = adt7475_read(REG_VTT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) data->voltage[INPUT][5] = ret << 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ((ext >> 4) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) for (i = 0; i < ADT7475_TACH_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (i == 3 && !data->has_fan4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ret = adt7475_read_word(client, TACH_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) data->tach[INPUT][i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) /* Updated by hw when in auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) for (i = 0; i < ADT7475_PWM_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (i == 1 && !data->has_pwm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ret = adt7475_read(PWM_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) data->pwm[INPUT][i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (data->has_vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) ret = adt7475_read(REG_VID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) data->vid = ret & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static struct adt7475_data *adt7475_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) struct adt7475_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* Measurement values update every 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (time_after(jiffies, data->measure_updated + HZ * 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ret = adt7475_update_measure(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) data->valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) data->measure_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) data->valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) module_i2c_driver(adt7475_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) MODULE_AUTHOR("Advanced Micro Devices, Inc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) MODULE_DESCRIPTION("adt7475 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags