^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the ADT7411 (I2C/SPI 8 channel 10 bit ADC & temperature-sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008, 2010 Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * TODO: SPI, use power-down mode for suspend?, interrupt handling?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADT7411_REG_STAT_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADT7411_STAT_1_INT_TEMP_HIGH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADT7411_STAT_1_INT_TEMP_LOW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADT7411_STAT_1_EXT_TEMP_HIGH_AIN1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADT7411_STAT_1_EXT_TEMP_LOW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADT7411_STAT_1_EXT_TEMP_FAULT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADT7411_STAT_1_AIN2 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADT7411_STAT_1_AIN3 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADT7411_STAT_1_AIN4 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADT7411_REG_STAT_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADT7411_STAT_2_AIN5 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADT7411_STAT_2_AIN6 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADT7411_STAT_2_AIN7 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADT7411_STAT_2_AIN8 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADT7411_STAT_2_VDD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADT7411_REG_INT_TEMP_VDD_LSB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADT7411_REG_EXT_TEMP_AIN14_LSB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADT7411_REG_VDD_MSB 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADT7411_REG_INT_TEMP_MSB 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADT7411_REG_EXT_TEMP_AIN1_MSB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADT7411_REG_CFG1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADT7411_CFG1_START_MONITOR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADT7411_CFG1_RESERVED_BIT1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADT7411_CFG1_EXT_TDM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADT7411_CFG1_RESERVED_BIT3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADT7411_REG_CFG2 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADT7411_CFG2_DISABLE_AVG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADT7411_REG_CFG3 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADT7411_CFG3_ADC_CLK_225 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADT7411_CFG3_RESERVED_BIT1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADT7411_CFG3_RESERVED_BIT2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADT7411_CFG3_RESERVED_BIT3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADT7411_CFG3_REF_VDD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADT7411_REG_VDD_HIGH 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADT7411_REG_VDD_LOW 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADT7411_REG_TEMP_HIGH(nr) (0x25 + 2 * (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADT7411_REG_TEMP_LOW(nr) (0x26 + 2 * (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADT7411_REG_IN_HIGH(nr) ((nr) > 1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ? 0x2b + 2 * ((nr)-2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) : 0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADT7411_REG_IN_LOW(nr) ((nr) > 1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ? 0x2c + 2 * ((nr)-2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) : 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADT7411_REG_DEVICE_ID 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADT7411_REG_MANUFACTURER_ID 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADT7411_DEVICE_ID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ADT7411_MANUFACTURER_ID 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const unsigned short normal_i2c[] = { 0x48, 0x4a, 0x4b, I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const u8 adt7411_in_alarm_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ADT7411_REG_STAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ADT7411_REG_STAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ADT7411_REG_STAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ADT7411_REG_STAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADT7411_REG_STAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ADT7411_REG_STAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ADT7411_REG_STAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ADT7411_REG_STAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ADT7411_REG_STAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const u8 adt7411_in_alarm_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ADT7411_STAT_2_VDD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ADT7411_STAT_1_EXT_TEMP_HIGH_AIN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ADT7411_STAT_1_AIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ADT7411_STAT_1_AIN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ADT7411_STAT_1_AIN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ADT7411_STAT_2_AIN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ADT7411_STAT_2_AIN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ADT7411_STAT_2_AIN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ADT7411_STAT_2_AIN8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct adt7411_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mutex device_lock; /* for "atomic" device accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long next_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) long vref_cached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool use_ext_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * When reading a register containing (up to 4) lsb, all associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * msb-registers get locked by the hardware. After _one_ of those msb is read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * _all_ are unlocked. In order to use this locking correctly, reading lsb/msb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * is protected here with a mutex, too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int adt7411_read_10_bit(struct i2c_client *client, u8 lsb_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 msb_reg, u8 lsb_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct adt7411_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int val, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mutex_lock(&data->device_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val = i2c_smbus_read_byte_data(client, lsb_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto exit_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) tmp = (val >> lsb_shift) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val = i2c_smbus_read_byte_data(client, msb_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (val >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val = (val << 2) | tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) exit_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mutex_unlock(&data->device_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int adt7411_modify_bit(struct i2c_client *client, u8 reg, u8 bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct adt7411_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mutex_lock(&data->device_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto exit_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = ret | bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val = ret & ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) exit_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mutex_unlock(&data->device_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static ssize_t adt7411_show_bit(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sensor_device_attribute_2 *attr2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret = i2c_smbus_read_byte_data(client, attr2->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret < 0 ? ret : sprintf(buf, "%u\n", !!(ret & attr2->nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static ssize_t adt7411_set_bit(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct sensor_device_attribute_2 *s_attr2 = to_sensor_dev_attr_2(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = kstrtoul(buf, 0, &flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret || flag > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = adt7411_modify_bit(client, s_attr2->index, s_attr2->nr, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* force update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) data->next_update = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret < 0 ? ret : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ADT7411_BIT_ATTR(__name, __reg, __bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SENSOR_DEVICE_ATTR_2(__name, S_IRUGO | S_IWUSR, adt7411_show_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) adt7411_set_bit, __bit, __reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static ADT7411_BIT_ATTR(no_average, ADT7411_REG_CFG2, ADT7411_CFG2_DISABLE_AVG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static ADT7411_BIT_ATTR(fast_sampling, ADT7411_REG_CFG3, ADT7411_CFG3_ADC_CLK_225);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static ADT7411_BIT_ATTR(adc_ref_vdd, ADT7411_REG_CFG3, ADT7411_CFG3_REF_VDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct attribute *adt7411_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) &sensor_dev_attr_no_average.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) &sensor_dev_attr_fast_sampling.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &sensor_dev_attr_adc_ref_vdd.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ATTRIBUTE_GROUPS(adt7411);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int adt7411_read_in_alarm(struct device *dev, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = i2c_smbus_read_byte_data(client, adt7411_in_alarm_reg[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *val = !!(ret & adt7411_in_alarm_bits[channel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int adt7411_read_in_vdd(struct device *dev, u32 attr, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = adt7411_read_10_bit(client, ADT7411_REG_INT_TEMP_VDD_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ADT7411_REG_VDD_MSB, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *val = ret * 7000 / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = i2c_smbus_read_byte_data(client, ADT7411_REG_VDD_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *val = ret * 7000 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = i2c_smbus_read_byte_data(client, ADT7411_REG_VDD_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *val = ret * 7000 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case hwmon_in_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return adt7411_read_in_alarm(dev, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int adt7411_update_vref(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (time_after_eq(jiffies, data->next_update)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val = i2c_smbus_read_byte_data(client, ADT7411_REG_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (val & ADT7411_CFG3_REF_VDD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val = adt7411_read_in_vdd(dev, hwmon_in_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &data->vref_cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) data->vref_cached = 2250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) data->next_update = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int adt7411_read_in_chan(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int reg, lsb_reg, lsb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int nr = channel - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = adt7411_update_vref(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto exit_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) lsb_reg = ADT7411_REG_EXT_TEMP_AIN14_LSB + (nr >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) lsb_shift = 2 * (nr & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = adt7411_read_10_bit(client, lsb_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ADT7411_REG_EXT_TEMP_AIN1_MSB + nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) lsb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto exit_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *val = ret * data->vref_cached / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) reg = (attr == hwmon_in_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ? ADT7411_REG_IN_LOW(channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) : ADT7411_REG_IN_HIGH(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto exit_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *val = ret * data->vref_cached / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case hwmon_in_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = adt7411_read_in_alarm(dev, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) exit_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int adt7411_read_in(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return adt7411_read_in_vdd(dev, attr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return adt7411_read_in_chan(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int adt7411_read_temp_alarm(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int ret, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = i2c_smbus_read_byte_data(client, ADT7411_REG_STAT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bit = channel ? ADT7411_STAT_1_EXT_TEMP_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) : ADT7411_STAT_1_INT_TEMP_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bit = channel ? ADT7411_STAT_1_EXT_TEMP_HIGH_AIN1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) : ADT7411_STAT_1_INT_TEMP_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bit = ADT7411_STAT_1_EXT_TEMP_FAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *val = !!(ret & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int adt7411_read_temp(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int ret, reg, regl, regh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regl = channel ? ADT7411_REG_EXT_TEMP_AIN14_LSB :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ADT7411_REG_INT_TEMP_VDD_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) regh = channel ? ADT7411_REG_EXT_TEMP_AIN1_MSB :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ADT7411_REG_INT_TEMP_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = adt7411_read_10_bit(client, regl, regh, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = ret & 0x200 ? ret - 0x400 : ret; /* 10 bit signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *val = ret * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reg = (attr == hwmon_temp_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ? ADT7411_REG_TEMP_LOW(channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) : ADT7411_REG_TEMP_HIGH(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = ret & 0x80 ? ret - 0x100 : ret; /* 8 bit signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *val = ret * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return adt7411_read_temp_alarm(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int adt7411_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return adt7411_read_in(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return adt7411_read_temp(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int adt7411_write_in_vdd(struct device *dev, u32 attr, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) val = clamp_val(val, 0, 255 * 7000 / 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) val = DIV_ROUND_CLOSEST(val * 256, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) reg = ADT7411_REG_VDD_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) reg = ADT7411_REG_VDD_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int adt7411_write_in_chan(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = adt7411_update_vref(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto exit_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val = clamp_val(val, 0, 255 * data->vref_cached / 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val = DIV_ROUND_CLOSEST(val * 256, data->vref_cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) reg = ADT7411_REG_IN_LOW(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) reg = ADT7411_REG_IN_HIGH(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto exit_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) exit_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int adt7411_write_in(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return adt7411_write_in_vdd(dev, attr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return adt7411_write_in_chan(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int adt7411_write_temp(struct device *dev, u32 attr, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct adt7411_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val = clamp_val(val, -128000, 127000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) val = DIV_ROUND_CLOSEST(val, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) reg = ADT7411_REG_TEMP_LOW(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) reg = ADT7411_REG_TEMP_HIGH(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int adt7411_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return adt7411_write_in(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return adt7411_write_temp(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static umode_t adt7411_is_visible(const void *_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) const struct adt7411_data *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) bool visible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) visible = channel == 0 || channel >= 3 || !data->use_ext_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case hwmon_in_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return visible ? S_IRUGO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return visible ? S_IRUGO | S_IWUSR : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) visible = channel == 0 || data->use_ext_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case hwmon_temp_fault:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return visible ? S_IRUGO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return visible ? S_IRUGO | S_IWUSR : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int adt7411_detect(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val = i2c_smbus_read_byte_data(client, ADT7411_REG_MANUFACTURER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (val < 0 || val != ADT7411_MANUFACTURER_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "Wrong manufacturer ID. Got %d, expected %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val, ADT7411_MANUFACTURER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) val = i2c_smbus_read_byte_data(client, ADT7411_REG_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (val < 0 || val != ADT7411_DEVICE_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "Wrong device ID. Got %d, expected %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) val, ADT7411_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) strlcpy(info->type, "adt7411", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int adt7411_init_device(struct adt7411_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = i2c_smbus_read_byte_data(data->client, ADT7411_REG_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * We must only write zero to bit 1 and bit 2 and only one to bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * according to the datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val &= ~(ADT7411_CFG3_RESERVED_BIT1 | ADT7411_CFG3_RESERVED_BIT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val |= ADT7411_CFG3_RESERVED_BIT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = i2c_smbus_write_byte_data(data->client, ADT7411_REG_CFG3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = i2c_smbus_read_byte_data(data->client, ADT7411_REG_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) data->use_ext_temp = ret & ADT7411_CFG1_EXT_TDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * We must only write zero to bit 1 and only one to bit 3 according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * the datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val &= ~ADT7411_CFG1_RESERVED_BIT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) val |= ADT7411_CFG1_RESERVED_BIT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* enable monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) val |= ADT7411_CFG1_START_MONITOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return i2c_smbus_write_byte_data(data->client, ADT7411_REG_CFG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const struct hwmon_channel_info *adt7411_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) HWMON_CHANNEL_INFO(in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | HWMON_I_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MIN_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) HWMON_T_MAX | HWMON_T_MAX_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MIN_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) HWMON_T_MAX | HWMON_T_MAX_ALARM | HWMON_T_FAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct hwmon_ops adt7411_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .is_visible = adt7411_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .read = adt7411_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .write = adt7411_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const struct hwmon_chip_info adt7411_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .ops = &adt7411_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .info = adt7411_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int adt7411_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct adt7411_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mutex_init(&data->device_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = adt7411_init_device(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* force update on first occasion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) data->next_update = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &adt7411_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) adt7411_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct i2c_device_id adt7411_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { "adt7411", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MODULE_DEVICE_TABLE(i2c, adt7411_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static struct i2c_driver adt7411_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "adt7411",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .probe_new = adt7411_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .id_table = adt7411_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .detect = adt7411_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) module_i2c_driver(adt7411_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MODULE_AUTHOR("Sascha Hauer, Wolfram Sang <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MODULE_DESCRIPTION("ADT7411 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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