^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ads7871 - driver for TI ADS7871 A/D converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010 Paul Thomas <pthomas8589@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * You need to have something like this in struct spi_board_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * .modalias = "ads7871",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * .max_speed_hz = 2*1000*1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * .bus_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*From figure 18 in the datasheet*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*Register addresses*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_LS_BYTE 0 /*A/D Output Data, LS Byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_MS_BYTE 1 /*A/D Output Data, MS Byte*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_PGA_VALID 2 /*PGA Valid Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_AD_CONTROL 3 /*A/D Control Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_GAIN_MUX 4 /*Gain/Mux Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_IO_STATE 5 /*Digital I/O State Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_IO_CONTROL 6 /*Digital I/O Control Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_OSC_CONTROL 7 /*Rev/Oscillator Control Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_SER_CONTROL 24 /*Serial Interface Control Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_ID 31 /*ID Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * From figure 17 in the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * These bits get ORed with the address to form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * the instruction byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*Instruction Bit masks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define INST_MODE_BM (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define INST_READ_BM (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define INST_16BIT_BM (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*From figure 18 in the datasheet*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*bit masks for Rev/Oscillator Control Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUX_CNV_BV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MUX_CNV_BM (1 << MUX_CNV_BV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MUX_M3_BM (1 << 3) /*M3 selects single ended*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MUX_G_BV 4 /*allows for reg = (gain << MUX_G_BV) | ...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*From figure 18 in the datasheet*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*bit masks for Rev/Oscillator Control Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OSC_OSCR_BM (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OSC_OSCE_BM (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OSC_REFE_BM (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OSC_BUFE_BM (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OSC_R2V_BM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OSC_RBG_BM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DEVICE_NAME "ads7871"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ads7871_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int ads7871_read_reg8(struct spi_device *spi, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = reg | INST_READ_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = spi_w8r8(spi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int ads7871_read_reg16(struct spi_device *spi, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg = reg | INST_READ_BM | INST_16BIT_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = spi_w8r16(spi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int ads7871_write_reg8(struct spi_device *spi, int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 tmp[2] = {reg, val};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return spi_write(spi, tmp, sizeof(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static ssize_t voltage_show(struct device *dev, struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ads7871_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct spi_device *spi = pdata->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int ret, val, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint8_t channel, mux_cnv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) channel = attr->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * TODO: add support for conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * other than single ended with a gain of 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*MUX_M3_BM forces single ended*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*This is also where the gain of the PGA would be set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ads7871_write_reg8(spi, REG_GAIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (MUX_CNV_BM | MUX_M3_BM | channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mux_cnv = ((ret & MUX_CNV_BM) >> MUX_CNV_BV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * on 400MHz arm9 platform the conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * is already done when we do this test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) while ((i < 2) && mux_cnv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mux_cnv = ((ret & MUX_CNV_BM) >> MUX_CNV_BV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) msleep_interruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (mux_cnv == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val = ads7871_read_reg16(spi, REG_LS_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*result in volts*10000 = (val/8192)*2.5*10000*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = ((val >> 2) * 25000) / 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static SENSOR_DEVICE_ATTR_RO(in0_input, voltage, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static SENSOR_DEVICE_ATTR_RO(in1_input, voltage, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static SENSOR_DEVICE_ATTR_RO(in2_input, voltage, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static SENSOR_DEVICE_ATTR_RO(in3_input, voltage, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static SENSOR_DEVICE_ATTR_RO(in4_input, voltage, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static SENSOR_DEVICE_ATTR_RO(in5_input, voltage, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static SENSOR_DEVICE_ATTR_RO(in6_input, voltage, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static SENSOR_DEVICE_ATTR_RO(in7_input, voltage, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct attribute *ads7871_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) &sensor_dev_attr_in0_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &sensor_dev_attr_in1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &sensor_dev_attr_in2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &sensor_dev_attr_in3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) &sensor_dev_attr_in4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &sensor_dev_attr_in5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) &sensor_dev_attr_in6_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &sensor_dev_attr_in7_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ATTRIBUTE_GROUPS(ads7871);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int ads7871_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) uint8_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct ads7871_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Configure the SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spi->mode = (SPI_MODE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ads7871_write_reg8(spi, REG_SER_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ads7871_write_reg8(spi, REG_AD_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = (OSC_OSCR_BM | OSC_OSCE_BM | OSC_REFE_BM | OSC_BUFE_BM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ads7871_write_reg8(spi, REG_OSC_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = ads7871_read_reg8(spi, REG_OSC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_dbg(dev, "REG_OSC_CONTROL write:%x, read:%x\n", val, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * because there is no other error checking on an SPI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * we need to make sure we really have a chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (val != ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pdata = devm_kzalloc(dev, sizeof(struct ads7871_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pdata->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) hwmon_dev = devm_hwmon_device_register_with_groups(dev, spi->modalias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ads7871_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct spi_driver ads7871_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .probe = ads7871_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) module_spi_driver(ads7871_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MODULE_AUTHOR("Paul Thomas <pthomas8589@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_DESCRIPTION("TI ADS7871 A/D driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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