^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for TI ADC128D818 System Monitor with Temperature Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Guenter Roeck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Derived from lm80.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and Philip Edelbrock <phil@netroedge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Addresses to scan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * The chip also supports addresses 0x35..0x37. Don't scan those addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * since they are also used by some EEPROMs, which may result in false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * positives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const unsigned short normal_i2c[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 0x1d, 0x1e, 0x1f, 0x2d, 0x2e, 0x2f, I2C_CLIENT_END };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADC128_REG_IN_MAX(nr) (0x2a + (nr) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADC128_REG_IN_MIN(nr) (0x2b + (nr) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADC128_REG_IN(nr) (0x20 + (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADC128_REG_TEMP 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADC128_REG_TEMP_MAX 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADC128_REG_TEMP_HYST 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADC128_REG_CONFIG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADC128_REG_ALARM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADC128_REG_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADC128_REG_CONV_RATE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADC128_REG_ONESHOT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADC128_REG_SHUTDOWN 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADC128_REG_CONFIG_ADV 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADC128_REG_BUSY_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADC128_REG_MAN_ID 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADC128_REG_DEV_ID 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* No. of voltage entries in adc128_attrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADC128_ATTR_NUM_VOLT (8 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Voltage inputs visible per operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const u8 num_inputs[] = { 7, 8, 4, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct adc128_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int vref; /* Reference voltage in mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mutex update_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 mode; /* Operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) bool valid; /* true if following fields are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long last_updated; /* In jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 in[3][8]; /* Register value, normalized to 12 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 0: input voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 1: min limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 2: max limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) s16 temp[3]; /* Register value, normalized to 9 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 0: sensor 1: limit 2: hyst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 alarms; /* alarm register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct adc128_data *adc128_update_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct adc128_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct adc128_data *ret = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int i, rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) for (i = 0; i < num_inputs[data->mode]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rv = i2c_smbus_read_word_swapped(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ADC128_REG_IN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) data->in[0][i] = rv >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rv = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ADC128_REG_IN_MIN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data->in[1][i] = rv << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rv = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ADC128_REG_IN_MAX(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) data->in[2][i] = rv << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (data->mode != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) rv = i2c_smbus_read_word_swapped(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ADC128_REG_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) data->temp[0] = rv >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rv = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ADC128_REG_TEMP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) data->temp[1] = rv << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rv = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ADC128_REG_TEMP_HYST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) data->temp[2] = rv << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rv = i2c_smbus_read_byte_data(client, ADC128_REG_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (rv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) data->alarms |= rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) data->last_updated = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data->valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = ERR_PTR(rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data->valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static ssize_t adc128_in_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct adc128_data *data = adc128_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int index = to_sensor_dev_attr_2(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int nr = to_sensor_dev_attr_2(attr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = DIV_ROUND_CLOSEST(data->in[index][nr] * data->vref, 4095);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return sprintf(buf, "%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static ssize_t adc128_in_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct adc128_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int index = to_sensor_dev_attr_2(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int nr = to_sensor_dev_attr_2(attr)->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 reg, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* 10 mV LSB on limit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) regval = clamp_val(DIV_ROUND_CLOSEST(val, 10), 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) data->in[index][nr] = regval << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reg = index == 1 ? ADC128_REG_IN_MIN(nr) : ADC128_REG_IN_MAX(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) i2c_smbus_write_byte_data(data->client, reg, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static ssize_t adc128_temp_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct adc128_data *data = adc128_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int index = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) temp = sign_extend32(data->temp[index], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return sprintf(buf, "%d\n", temp * 500);/* 0.5 degrees C resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static ssize_t adc128_temp_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct adc128_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int index = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) s8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) err = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mutex_lock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) regval = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) data->temp[index] = regval << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) index == 1 ? ADC128_REG_TEMP_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) : ADC128_REG_TEMP_HYST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mutex_unlock(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static ssize_t adc128_alarm_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct adc128_data *data = adc128_update_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int mask = 1 << to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return PTR_ERR(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Clear an alarm after reporting it to user space. If it is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * active, the next update sequence will set the alarm bit again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) alarms = data->alarms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) data->alarms &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return sprintf(buf, "%u\n", !!(alarms & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static umode_t adc128_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct device *dev = container_of(kobj, struct device, kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct adc128_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (index < ADC128_ATTR_NUM_VOLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Voltage, visible according to num_inputs[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (index >= num_inputs[data->mode] * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Temperature, visible if not in mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (data->mode == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static SENSOR_DEVICE_ATTR_2_RO(in0_input, adc128_in, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static SENSOR_DEVICE_ATTR_2_RW(in0_min, adc128_in, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static SENSOR_DEVICE_ATTR_2_RW(in0_max, adc128_in, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static SENSOR_DEVICE_ATTR_2_RO(in1_input, adc128_in, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static SENSOR_DEVICE_ATTR_2_RW(in1_min, adc128_in, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static SENSOR_DEVICE_ATTR_2_RW(in1_max, adc128_in, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static SENSOR_DEVICE_ATTR_2_RO(in2_input, adc128_in, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static SENSOR_DEVICE_ATTR_2_RW(in2_min, adc128_in, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static SENSOR_DEVICE_ATTR_2_RW(in2_max, adc128_in, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static SENSOR_DEVICE_ATTR_2_RO(in3_input, adc128_in, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static SENSOR_DEVICE_ATTR_2_RW(in3_min, adc128_in, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static SENSOR_DEVICE_ATTR_2_RW(in3_max, adc128_in, 3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SENSOR_DEVICE_ATTR_2_RO(in4_input, adc128_in, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static SENSOR_DEVICE_ATTR_2_RW(in4_min, adc128_in, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static SENSOR_DEVICE_ATTR_2_RW(in4_max, adc128_in, 4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static SENSOR_DEVICE_ATTR_2_RO(in5_input, adc128_in, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static SENSOR_DEVICE_ATTR_2_RW(in5_min, adc128_in, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static SENSOR_DEVICE_ATTR_2_RW(in5_max, adc128_in, 5, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static SENSOR_DEVICE_ATTR_2_RO(in6_input, adc128_in, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static SENSOR_DEVICE_ATTR_2_RW(in6_min, adc128_in, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static SENSOR_DEVICE_ATTR_2_RW(in6_max, adc128_in, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static SENSOR_DEVICE_ATTR_2_RO(in7_input, adc128_in, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static SENSOR_DEVICE_ATTR_2_RW(in7_min, adc128_in, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static SENSOR_DEVICE_ATTR_2_RW(in7_max, adc128_in, 7, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static SENSOR_DEVICE_ATTR_RO(temp1_input, adc128_temp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static SENSOR_DEVICE_ATTR_RW(temp1_max, adc128_temp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static SENSOR_DEVICE_ATTR_RW(temp1_max_hyst, adc128_temp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static SENSOR_DEVICE_ATTR_RO(in0_alarm, adc128_alarm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static SENSOR_DEVICE_ATTR_RO(in1_alarm, adc128_alarm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static SENSOR_DEVICE_ATTR_RO(in2_alarm, adc128_alarm, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static SENSOR_DEVICE_ATTR_RO(in3_alarm, adc128_alarm, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static SENSOR_DEVICE_ATTR_RO(in4_alarm, adc128_alarm, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static SENSOR_DEVICE_ATTR_RO(in5_alarm, adc128_alarm, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static SENSOR_DEVICE_ATTR_RO(in6_alarm, adc128_alarm, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static SENSOR_DEVICE_ATTR_RO(in7_alarm, adc128_alarm, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static SENSOR_DEVICE_ATTR_RO(temp1_max_alarm, adc128_alarm, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct attribute *adc128_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &sensor_dev_attr_in0_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) &sensor_dev_attr_in0_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) &sensor_dev_attr_in0_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) &sensor_dev_attr_in0_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) &sensor_dev_attr_in1_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) &sensor_dev_attr_in1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) &sensor_dev_attr_in1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) &sensor_dev_attr_in1_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) &sensor_dev_attr_in2_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) &sensor_dev_attr_in2_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) &sensor_dev_attr_in2_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) &sensor_dev_attr_in2_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) &sensor_dev_attr_in3_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) &sensor_dev_attr_in3_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) &sensor_dev_attr_in3_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) &sensor_dev_attr_in3_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) &sensor_dev_attr_in4_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &sensor_dev_attr_in4_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) &sensor_dev_attr_in4_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) &sensor_dev_attr_in4_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) &sensor_dev_attr_in5_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &sensor_dev_attr_in5_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) &sensor_dev_attr_in5_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) &sensor_dev_attr_in5_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) &sensor_dev_attr_in6_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) &sensor_dev_attr_in6_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) &sensor_dev_attr_in6_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) &sensor_dev_attr_in6_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) &sensor_dev_attr_in7_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) &sensor_dev_attr_in7_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) &sensor_dev_attr_in7_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) &sensor_dev_attr_in7_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) &sensor_dev_attr_temp1_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct attribute_group adc128_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .attrs = adc128_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .is_visible = adc128_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) __ATTRIBUTE_GROUPS(adc128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int adc128_detect(struct i2c_client *client, struct i2c_board_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int man_id, dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) I2C_FUNC_SMBUS_WORD_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) man_id = i2c_smbus_read_byte_data(client, ADC128_REG_MAN_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_id = i2c_smbus_read_byte_data(client, ADC128_REG_DEV_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (man_id != 0x01 || dev_id != 0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Check unused bits for confirmation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (i2c_smbus_read_byte_data(client, ADC128_REG_CONFIG) & 0xf4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (i2c_smbus_read_byte_data(client, ADC128_REG_CONV_RATE) & 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (i2c_smbus_read_byte_data(client, ADC128_REG_ONESHOT) & 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (i2c_smbus_read_byte_data(client, ADC128_REG_SHUTDOWN) & 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (i2c_smbus_read_byte_data(client, ADC128_REG_CONFIG_ADV) & 0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (i2c_smbus_read_byte_data(client, ADC128_REG_BUSY_STATUS) & 0xfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) strlcpy(info->type, "adc128d818", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int adc128_init_client(struct adc128_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 regval = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Reset chip to defaults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * This makes most other initializations unnecessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Set operation mode, if non-default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (data->mode != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) regval |= data->mode << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* If external vref is selected, configure the chip to use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (data->regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) regval |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Write advanced configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (regval != 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG_ADV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Start monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int adc128_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct adc128_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int err, vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) data = devm_kzalloc(dev, sizeof(struct adc128_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* vref is optional. If specified, is used as chip reference voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) regulator = devm_regulator_get_optional(dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!IS_ERR(regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) data->regulator = regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = regulator_enable(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) vref = regulator_get_voltage(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (vref < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) err = vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) data->vref = DIV_ROUND_CLOSEST(vref, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) data->vref = 2560; /* 2.56V, in mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Operation mode is optional. If unspecified, keep current mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (of_property_read_u8(dev->of_node, "ti,mode", &data->mode) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (data->mode > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(dev, "invalid operation mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) data->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) err = i2c_smbus_read_byte_data(client, ADC128_REG_CONFIG_ADV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) data->mode = (err >> 1) & ADC128_REG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mutex_init(&data->update_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Initialize the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) err = adc128_init_client(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) data, adc128_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) err = PTR_ERR(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (data->regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) regulator_disable(data->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int adc128_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct adc128_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (data->regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) regulator_disable(data->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct i2c_device_id adc128_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { "adc128d818", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_DEVICE_TABLE(i2c, adc128_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct of_device_id __maybe_unused adc128_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { .compatible = "ti,adc128d818" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_DEVICE_TABLE(of, adc128_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct i2c_driver adc128_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .name = "adc128d818",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .of_match_table = of_match_ptr(adc128_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .probe_new = adc128_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .remove = adc128_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .id_table = adc128_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .detect = adc128_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .address_list = normal_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) module_i2c_driver(adc128_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_AUTHOR("Guenter Roeck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MODULE_DESCRIPTION("Driver for ADC128D818");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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