^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Most ISHTP provider device and ISHTP logic declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2003-2016, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ISHTP_DEV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ISHTP_DEV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "bus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "hbm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IPC_PAYLOAD_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ISHTP_RD_MSG_BUF_SIZE IPC_PAYLOAD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IPC_FULL_MSG_SIZE 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Number of messages to be held in ISR->BH FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RD_INT_FIFO_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Number of IPC messages to be held in Tx FIFO, to be sent by ISR -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Tx complete interrupt or RX_COMPLETE handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPC_TX_FIFO_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Number of Maximum ISHTP Clients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ISHTP_CLIENTS_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Number of File descriptors/handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * that can be opened to the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Limit to 255: 256 Total Clients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * minus internal client for ISHTP Bus Messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ISHTP_MAX_OPEN_HANDLE_COUNT (ISHTP_CLIENTS_MAX - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Internal Clients Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ISHTP_HOST_CLIENT_ID_ANY (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ISHTP_HBM_HOST_CLIENT_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX_DMA_DELAY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* ISHTP device states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum ishtp_dev_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ISHTP_DEV_INITIALIZING = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ISHTP_DEV_INIT_CLIENTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ISHTP_DEV_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ISHTP_DEV_RESETTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ISHTP_DEV_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ISHTP_DEV_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ISHTP_DEV_POWER_UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const char *ishtp_dev_state_str(int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct ishtp_cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * struct ishtp_fw_client - representation of fw client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @props - client properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @client_id - fw client id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct ishtp_fw_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct ishtp_client_properties props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) uint8_t client_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Control info for IPC messages ISHTP/IPC sending FIFO -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * list with inline data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * This structure will be filled with parameters submitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * by the caller glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 'buf' may be pointing to the external buffer or to 'inline_data'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 'offset' will be initialized to 0 by submitting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 'ipc_send_compl' is intended for use by clients that send fragmented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * messages. When a fragment is sent down to IPC msg regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * it will be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * If it has more fragments to send, it will do it. With last fragment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * it will send appropriate ISHTP "message-complete" flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * It will remove the outstanding message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * (mark outstanding buffer as available).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * If counting flow control is in work and there are more flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * credits, it can put the next client message queued in cl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * structure for IPC processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct wr_msg_ctl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Will be called with 'ipc_send_compl_prm' as parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void (*ipc_send_compl)(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void *ipc_send_compl_prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct list_head link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned char inline_data[IPC_FULL_MSG_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * The ISHTP layer talks to hardware IPC message using the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ishtp_hw_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int (*hw_reset)(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int (*ipc_reset)(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint32_t (*ipc_get_header)(struct ishtp_device *dev, int length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int (*write)(struct ishtp_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void (*ipc_send_compl)(void *), void *ipc_send_compl_prm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned char *msg, int length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint32_t (*ishtp_read_hdr)(const struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int (*ishtp_read)(struct ishtp_device *dev, unsigned char *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) uint32_t (*get_fw_status)(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void (*sync_fw_clock)(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * struct ishtp_device - ISHTP private device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct ishtp_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct device *devc; /* pointer to lowest device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pci_dev *pdev; /* PCI device to get device ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* waitq for waiting for suspend response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wait_queue_head_t suspend_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool suspend_flag; /* Suspend is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* waitq for waiting for resume response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) wait_queue_head_t resume_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool resume_flag; /*Resume is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * lock for the device, for everything that doesn't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * a dedicated spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spinlock_t device_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bool recvd_hw_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct hbm_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int transfer_path; /* Choice of transfer path: IPC or DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* ishtp device states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum ishtp_dev_state dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum ishtp_hbm_state hbm_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* driver read queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ishtp_cl_rb read_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spinlock_t read_list_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* list of ishtp_cl's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct list_head cl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spinlock_t cl_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) long open_handle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* List of bus devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct list_head device_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spinlock_t device_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* waiting queues for receive message from FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) wait_queue_head_t wait_hw_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) wait_queue_head_t wait_hbm_recvd_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* FIFO for input messages for BH processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned char rd_msg_fifo[RD_INT_FIFO_SIZE * IPC_PAYLOAD_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int rd_msg_fifo_head, rd_msg_fifo_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) spinlock_t rd_msg_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct work_struct bh_hbm_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* IPC write queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct list_head wr_processing_list, wr_free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* For both processing list and free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) spinlock_t wr_processing_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct ishtp_fw_client *fw_clients; /*Note:memory has to be allocated*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DECLARE_BITMAP(fw_clients_map, ISHTP_CLIENTS_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DECLARE_BITMAP(host_clients_map, ISHTP_CLIENTS_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) uint8_t fw_clients_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) uint8_t fw_client_presentation_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) uint8_t fw_client_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spinlock_t fw_clients_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* TX DMA buffers and slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ishtp_host_dma_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void *ishtp_host_dma_tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int ishtp_host_dma_tx_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint64_t ishtp_host_dma_tx_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int ishtp_dma_num_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* map of 4k blocks in Tx dma buf: 0-free, 1-used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) uint8_t *ishtp_dma_tx_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spinlock_t ishtp_dma_tx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* RX DMA buffers and slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void *ishtp_host_dma_rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int ishtp_host_dma_rx_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) uint64_t ishtp_host_dma_rx_buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Dump to trace buffers if enabled*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __printf(2, 3) void (*print_log)(struct ishtp_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const char *format, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Debug stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int ipc_rx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long long ipc_rx_bytes_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int ipc_tx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned long long ipc_tx_bytes_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const struct ishtp_hw_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) size_t mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint32_t ishtp_msg_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) char hw[] __aligned(sizeof(void *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline unsigned long ishtp_secs_to_jiffies(unsigned long sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return msecs_to_jiffies(sec * MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Register Access Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline int ish_ipc_reset(struct ishtp_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return dev->ops->ipc_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Exported function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void ishtp_device_init(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ishtp_start(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif /*_ISHTP_DEV_H_*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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