^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * H/W layer of ISHTP provider device (ISH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014-2016, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ISHTP_HW_ISH_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ISHTP_HW_ISH_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "hw-ish-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ishtp-dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CHV_DEVICE_ID 0x22D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BXT_Ax_DEVICE_ID 0x0AA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BXT_Bx_DEVICE_ID 0x1AA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define APL_Ax_DEVICE_ID 0x5AA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPT_Ax_DEVICE_ID 0x9D35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CNL_Ax_DEVICE_ID 0x9DFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GLK_Ax_DEVICE_ID 0x31A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CNL_H_DEVICE_ID 0xA37C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ICL_MOBILE_DEVICE_ID 0x34FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPT_H_DEVICE_ID 0xA135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CML_LP_DEVICE_ID 0x02FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CMP_H_DEVICE_ID 0x06FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EHL_Ax_DEVICE_ID 0x4BB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TGL_LP_DEVICE_ID 0xA0FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REVISION_ID_CHT_A0 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REVISION_ID_CHT_Ax_SI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REVISION_ID_CHT_Bx_SI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REVISION_ID_CHT_Kx_SI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REVISION_ID_CHT_Dx_SI 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REVISION_ID_CHT_B0 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REVISION_ID_SI_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ipc_rst_payload_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) uint16_t reset_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct time_sync_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) uint8_t ts1_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uint8_t ts2_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ipc_time_update_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uint64_t primary_host_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct time_sync_format sync_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) uint64_t secondary_host_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) HOST_UTC_TIME_USEC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) HOST_SYSTEM_TIME_USEC = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct ish_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * ISH FW status type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FWSTS_AFTER_RESET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FWSTS_WAIT_FOR_HOST = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FWSTS_START_KERNEL_DMA = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FWSTS_FW_IS_RUNNING = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FWSTS_SENSOR_APP_LOADED = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FWSTS_SENSOR_APP_RUNNING = 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) irqreturn_t ish_irq_handler(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ish_hw_start(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void ish_device_disable(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ish_disable_dma(struct ishtp_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif /* _ISHTP_HW_ISH_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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