^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MCP2221A - Microchip USB to I2C Host Protocol Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020, Rishi Gupta <gupt21@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005565B.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/hid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hidraw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "hid-ids.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Commands codes in a raw output report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MCP2221_I2C_WR_DATA = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MCP2221_I2C_WR_NO_STOP = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MCP2221_I2C_RD_DATA = 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MCP2221_I2C_RD_RPT_START = 0x93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MCP2221_I2C_GET_DATA = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MCP2221_I2C_PARAM_OR_STATUS = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MCP2221_I2C_SET_SPEED = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MCP2221_I2C_CANCEL = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MCP2221_GPIO_SET = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MCP2221_GPIO_GET = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Response codes in a raw input report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MCP2221_SUCCESS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MCP2221_I2C_ENG_BUSY = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MCP2221_I2C_START_TOUT = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MCP2221_I2C_STOP_TOUT = 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MCP2221_I2C_WRADDRL_TOUT = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MCP2221_I2C_WRDATA_TOUT = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MCP2221_I2C_WRADDRL_NACK = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MCP2221_I2C_MASK_ADDR_NACK = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MCP2221_I2C_WRADDRL_SEND = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MCP2221_I2C_ADDR_NACK = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MCP2221_I2C_READ_COMPL = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MCP2221_ALT_F_NOT_GPIOV = 0xEE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MCP2221_ALT_F_NOT_GPIOD = 0xEF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* MCP GPIO direction encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MCP2221_DIR_OUT = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MCP2221_DIR_IN = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCP_NGPIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* MCP GPIO set command layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct mcp_set_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 change_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 change_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } gpio[MCP_NGPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* MCP GPIO get command layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mcp_get_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } gpio[MCP_NGPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * There is no way to distinguish responses. Therefore next command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * is sent only after response to previous has been received. Mutex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * lock is used for this purpose mainly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct mcp2221 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct hid_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct completion wait_in_report;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 *rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 txbuf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int rxbuf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 cur_i2c_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 gp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Default i2c bus clock frequency 400 kHz. Modify this if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * want to set some other frequency (min 50 kHz - max 400 kHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static uint i2c_clk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Synchronously send output report to the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int mcp_send_report(struct mcp2221 *mcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 *out_report, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) buf = kmemdup(out_report, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* mcp2221 uses interrupt endpoint for out reports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = hid_hw_output_report(mcp->hdev, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Send o/p report to the device and wait for i/p report to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * received from the device. If the device does not respond,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * we timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int mcp_send_data_req_status(struct mcp2221 *mcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 *out_report, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reinit_completion(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = mcp_send_report(mcp, out_report, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) t = wait_for_completion_timeout(&mcp->wait_in_report,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) msecs_to_jiffies(4000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return mcp->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Check pass/fail for actual communication with i2c slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int mcp_chk_last_cmd_status(struct mcp2221 *mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) memset(mcp->txbuf, 0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mcp->txbuf[0] = MCP2221_I2C_PARAM_OR_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return mcp_send_data_req_status(mcp, mcp->txbuf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Cancels last command releasing i2c bus just in case occupied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int mcp_cancel_last_cmd(struct mcp2221 *mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) memset(mcp->txbuf, 0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mcp->txbuf[0] = MCP2221_I2C_PARAM_OR_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mcp->txbuf[2] = MCP2221_I2C_CANCEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return mcp_send_data_req_status(mcp, mcp->txbuf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int mcp_set_i2c_speed(struct mcp2221 *mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) memset(mcp->txbuf, 0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mcp->txbuf[0] = MCP2221_I2C_PARAM_OR_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mcp->txbuf[3] = MCP2221_I2C_SET_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mcp->txbuf[4] = mcp->cur_i2c_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = mcp_send_data_req_status(mcp, mcp->txbuf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Small delay is needed here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) usleep_range(980, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mcp_cancel_last_cmd(mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * An output report can contain minimum 1 and maximum 60 user data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * bytes. If the number of data bytes is more then 60, we send it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * in chunks of 60 bytes. Last chunk may contain exactly 60 or less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * bytes. Total number of bytes is informed in very first report to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * mcp2221, from that point onwards it first collect all the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * from host and then send to i2c slave device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int mcp_i2c_write(struct mcp2221 *mcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct i2c_msg *msg, int type, u8 last_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret, len, idx, sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (msg->len < 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) len = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mcp->txbuf[0] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mcp->txbuf[1] = msg->len & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mcp->txbuf[2] = msg->len >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mcp->txbuf[3] = (u8)(msg->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) memcpy(&mcp->txbuf[4], &msg->buf[idx], len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = mcp_send_data_req_status(mcp, mcp->txbuf, len + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) usleep_range(980, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (last_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = mcp_chk_last_cmd_status(mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sent = sent + len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (sent >= msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) idx = idx + len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if ((msg->len - sent) < 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) len = msg->len - sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) len = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Testing shows delay is needed between successive writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * otherwise next write fails on first-try from i2c core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * This value is obtained through automated stress testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) usleep_range(980, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } while (len > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Device reads all data (0 - 65535 bytes) from i2c slave device and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * stores it in device itself. This data is read back from device to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * host in multiples of 60 bytes using input reports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int mcp_i2c_smbus_read(struct mcp2221 *mcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct i2c_msg *msg, int type, u16 smbus_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 smbus_len, u8 *smbus_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u16 total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mcp->txbuf[0] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mcp->txbuf[1] = msg->len & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mcp->txbuf[2] = msg->len >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mcp->txbuf[3] = (u8)(msg->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) total_len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mcp->rxbuf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mcp->txbuf[1] = smbus_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mcp->txbuf[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mcp->txbuf[3] = (u8)(smbus_addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) total_len = smbus_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mcp->rxbuf = smbus_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = mcp_send_data_req_status(mcp, mcp->txbuf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mcp->rxbuf_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) memset(mcp->txbuf, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mcp->txbuf[0] = MCP2221_I2C_GET_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = mcp_send_data_req_status(mcp, mcp->txbuf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = mcp_chk_last_cmd_status(mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) usleep_range(980, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } while (mcp->rxbuf_idx < total_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int mcp_i2c_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mcp2221 *mcp = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hid_hw_power(mcp->hdev, PM_HINT_FULLON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Setting speed before every transaction is required for mcp2221 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = mcp_set_i2c_speed(mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (num == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (msgs->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = mcp_i2c_smbus_read(mcp, msgs, MCP2221_I2C_RD_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = mcp_i2c_write(mcp, msgs, MCP2221_I2C_WR_DATA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } else if (num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Ex transaction; send reg address and read its contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (msgs[0].addr == msgs[1].addr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) !(msgs[0].flags & I2C_M_RD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (msgs[1].flags & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = mcp_i2c_write(mcp, &msgs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MCP2221_I2C_WR_NO_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = mcp_i2c_smbus_read(mcp, &msgs[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MCP2221_I2C_RD_RPT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "unsupported multi-msg i2c transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "unsupported multi-msg i2c transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hid_hw_power(mcp->hdev, PM_HINT_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int mcp_smbus_write(struct mcp2221 *mcp, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 command, u8 *buf, u8 len, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 last_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int data_len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mcp->txbuf[0] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mcp->txbuf[1] = len + 1; /* 1 is due to command byte itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mcp->txbuf[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mcp->txbuf[3] = (u8)(addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mcp->txbuf[4] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) data_len = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mcp->txbuf[5] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) data_len = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mcp->txbuf[5] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mcp->txbuf[6] = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) data_len = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) memcpy(&mcp->txbuf[5], buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) data_len = len + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = mcp_send_data_req_status(mcp, mcp->txbuf, data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (last_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) usleep_range(980, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = mcp_chk_last_cmd_status(mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int mcp_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 command, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct mcp2221 *mcp = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) hid_hw_power(mcp->hdev, PM_HINT_FULLON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = mcp_set_i2c_speed(mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = mcp_i2c_smbus_read(mcp, NULL, MCP2221_I2C_RD_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) addr, 0, &data->byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = mcp_smbus_write(mcp, addr, command, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0, MCP2221_I2C_WR_DATA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = mcp_i2c_smbus_read(mcp, NULL, MCP2221_I2C_RD_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) addr, 1, &data->byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = mcp_smbus_write(mcp, addr, command, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0, MCP2221_I2C_WR_DATA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = mcp_smbus_write(mcp, addr, command, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0, MCP2221_I2C_WR_NO_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = mcp_i2c_smbus_read(mcp, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MCP2221_I2C_RD_RPT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) addr, 1, &data->byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = mcp_smbus_write(mcp, addr, command, &data->byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 1, MCP2221_I2C_WR_DATA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = mcp_smbus_write(mcp, addr, command, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0, MCP2221_I2C_WR_NO_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = mcp_i2c_smbus_read(mcp, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MCP2221_I2C_RD_RPT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) addr, 2, (u8 *)&data->word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = mcp_smbus_write(mcp, addr, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) (u8 *)&data->word, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MCP2221_I2C_WR_DATA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = mcp_smbus_write(mcp, addr, command, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0, MCP2221_I2C_WR_NO_STOP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mcp->rxbuf_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mcp->rxbuf = data->block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mcp->txbuf[0] = MCP2221_I2C_GET_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = mcp_send_data_req_status(mcp, mcp->txbuf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (!data->block[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = mcp_smbus_write(mcp, addr, command, data->block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) data->block[0] + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MCP2221_I2C_WR_DATA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = mcp_smbus_write(mcp, addr, command, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 0, MCP2221_I2C_WR_NO_STOP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mcp->rxbuf_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mcp->rxbuf = data->block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mcp->txbuf[0] = MCP2221_I2C_GET_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = mcp_send_data_req_status(mcp, mcp->txbuf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!data->block[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = mcp_smbus_write(mcp, addr, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &data->block[1], data->block[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MCP2221_I2C_WR_DATA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = mcp_smbus_write(mcp, addr, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) (u8 *)&data->word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 2, MCP2221_I2C_WR_NO_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = mcp_i2c_smbus_read(mcp, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MCP2221_I2C_RD_RPT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) addr, 2, (u8 *)&data->word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = mcp_smbus_write(mcp, addr, command, data->block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) data->block[0] + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MCP2221_I2C_WR_NO_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = mcp_i2c_smbus_read(mcp, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MCP2221_I2C_RD_RPT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) addr, I2C_SMBUS_BLOCK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) data->block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_err(&mcp->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "unsupported smbus transaction size:%d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hid_hw_power(mcp->hdev, PM_HINT_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static u32 mcp_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) I2C_FUNC_SMBUS_READ_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_PEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const struct i2c_algorithm mcp_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .master_xfer = mcp_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .smbus_xfer = mcp_smbus_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .functionality = mcp_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int mcp_gpio_get(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct mcp2221 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mcp->txbuf[0] = MCP2221_GPIO_GET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) mcp->gp_idx = offsetof(struct mcp_get_gpio, gpio[offset].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = mcp_send_data_req_status(mcp, mcp->txbuf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void mcp_gpio_set(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct mcp2221 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) memset(mcp->txbuf, 0, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mcp->txbuf[0] = MCP2221_GPIO_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mcp->gp_idx = offsetof(struct mcp_set_gpio, gpio[offset].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mcp->txbuf[mcp->gp_idx - 1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mcp->txbuf[mcp->gp_idx] = !!value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mcp_send_data_req_status(mcp, mcp->txbuf, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int mcp_gpio_dir_set(struct mcp2221 *mcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int offset, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) memset(mcp->txbuf, 0, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mcp->txbuf[0] = MCP2221_GPIO_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mcp->gp_idx = offsetof(struct mcp_set_gpio, gpio[offset].direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mcp->txbuf[mcp->gp_idx - 1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mcp->txbuf[mcp->gp_idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return mcp_send_data_req_status(mcp, mcp->txbuf, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int mcp_gpio_direction_input(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct mcp2221 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = mcp_gpio_dir_set(mcp, offset, MCP2221_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int mcp_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct mcp2221 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = mcp_gpio_dir_set(mcp, offset, MCP2221_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Can't configure as output, bailout early */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mcp_gpio_set(gc, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int mcp_gpio_get_direction(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct mcp2221 *mcp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mcp->txbuf[0] = MCP2221_GPIO_GET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mcp->gp_idx = offsetof(struct mcp_get_gpio, gpio[offset].direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mutex_lock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = mcp_send_data_req_status(mcp, mcp->txbuf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mutex_unlock(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (mcp->gpio_dir == MCP2221_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Gives current state of i2c engine inside mcp2221 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int mcp_get_i2c_eng_state(struct mcp2221 *mcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 *data, u8 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) switch (data[idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case MCP2221_I2C_WRADDRL_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case MCP2221_I2C_WRADDRL_SEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case MCP2221_I2C_START_TOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case MCP2221_I2C_STOP_TOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case MCP2221_I2C_WRADDRL_TOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case MCP2221_I2C_WRDATA_TOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case MCP2221_I2C_ENG_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case MCP2221_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * MCP2221 uses interrupt endpoint for input reports. This function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * is called by HID layer when it receives i/p report from mcp2221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * which is actually a response to the previously sent command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * MCP2221A firmware specific return codes are parsed and 0 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * appropriate negative error code is returned. Delayed response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * results in timeout error and stray reponses results in -EIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int mcp2221_raw_event(struct hid_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct hid_report *report, u8 *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct mcp2221 *mcp = hid_get_drvdata(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) switch (data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case MCP2221_I2C_WR_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case MCP2221_I2C_WR_NO_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case MCP2221_I2C_RD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case MCP2221_I2C_RD_RPT_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) switch (data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case MCP2221_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mcp->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mcp->status = mcp_get_i2c_eng_state(mcp, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) complete(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case MCP2221_I2C_PARAM_OR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) switch (data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case MCP2221_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if ((mcp->txbuf[3] == MCP2221_I2C_SET_SPEED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (data[3] != MCP2221_I2C_SET_SPEED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mcp->status = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (data[20] & MCP2221_I2C_MASK_ADDR_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mcp->status = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mcp->status = mcp_get_i2c_eng_state(mcp, data, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mcp->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) complete(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case MCP2221_I2C_GET_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) switch (data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case MCP2221_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (data[2] == MCP2221_I2C_ADDR_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mcp->status = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!mcp_get_i2c_eng_state(mcp, data, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) && (data[3] == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mcp->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (data[3] == 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mcp->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (data[2] == MCP2221_I2C_READ_COMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) buf = mcp->rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) memcpy(&buf[mcp->rxbuf_idx], &data[4], data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mcp->rxbuf_idx = mcp->rxbuf_idx + data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mcp->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mcp->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mcp->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) complete(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case MCP2221_GPIO_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) switch (data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case MCP2221_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if ((data[mcp->gp_idx] == MCP2221_ALT_F_NOT_GPIOV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) (data[mcp->gp_idx + 1] == MCP2221_ALT_F_NOT_GPIOD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mcp->status = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mcp->status = !!data[mcp->gp_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mcp->gpio_dir = data[mcp->gp_idx + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mcp->status = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) complete(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case MCP2221_GPIO_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) switch (data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case MCP2221_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if ((data[mcp->gp_idx] == MCP2221_ALT_F_NOT_GPIOV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) (data[mcp->gp_idx - 1] == MCP2221_ALT_F_NOT_GPIOV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mcp->status = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mcp->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mcp->status = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) complete(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mcp->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) complete(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int mcp2221_probe(struct hid_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) const struct hid_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct mcp2221 *mcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mcp = devm_kzalloc(&hdev->dev, sizeof(*mcp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = hid_parse(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) hid_err(hdev, "can't parse reports\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ret = hid_hw_start(hdev, HID_CONNECT_HIDRAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) hid_err(hdev, "can't start hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = hid_hw_open(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) hid_err(hdev, "can't open device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) goto err_hstop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mutex_init(&mcp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) init_completion(&mcp->wait_in_report);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) hid_set_drvdata(hdev, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) mcp->hdev = hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Set I2C bus clock diviser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (i2c_clk_freq > 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) i2c_clk_freq = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (i2c_clk_freq < 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) i2c_clk_freq = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mcp->cur_i2c_clk_div = (12000000 / (i2c_clk_freq * 1000)) - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mcp->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mcp->adapter.class = I2C_CLASS_HWMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mcp->adapter.algo = &mcp_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) mcp->adapter.retries = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mcp->adapter.dev.parent = &hdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) snprintf(mcp->adapter.name, sizeof(mcp->adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "MCP2221 usb-i2c bridge on hidraw%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ((struct hidraw *)hdev->hidraw)->minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = i2c_add_adapter(&mcp->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) hid_err(hdev, "can't add usb-i2c adapter: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) i2c_set_adapdata(&mcp->adapter, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Setup GPIO chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mcp->gc = devm_kzalloc(&hdev->dev, sizeof(*mcp->gc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (!mcp->gc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto err_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) mcp->gc->label = "mcp2221_gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) mcp->gc->direction_input = mcp_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) mcp->gc->direction_output = mcp_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) mcp->gc->get_direction = mcp_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mcp->gc->set = mcp_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mcp->gc->get = mcp_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) mcp->gc->ngpio = MCP_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) mcp->gc->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mcp->gc->can_sleep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) mcp->gc->parent = &hdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = devm_gpiochip_add_data(&hdev->dev, mcp->gc, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) goto err_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) err_gc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) i2c_del_adapter(&mcp->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) err_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) hid_hw_close(mcp->hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) err_hstop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) hid_hw_stop(mcp->hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static void mcp2221_remove(struct hid_device *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct mcp2221 *mcp = hid_get_drvdata(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) i2c_del_adapter(&mcp->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) hid_hw_close(mcp->hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) hid_hw_stop(mcp->hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const struct hid_device_id mcp2221_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_MCP2221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MODULE_DEVICE_TABLE(hid, mcp2221_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static struct hid_driver mcp2221_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .name = "mcp2221",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .id_table = mcp2221_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .probe = mcp2221_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .remove = mcp2221_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .raw_event = mcp2221_raw_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Register with HID core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) module_hid_driver(mcp2221_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) MODULE_AUTHOR("Rishi Gupta <gupt21@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) MODULE_DESCRIPTION("MCP2221 Microchip HID USB to I2C master bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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