Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __IPU_PRV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __IPU_PRV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) struct ipu_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IPU_MCU_T_DEFAULT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IPU_CM_IDMAC_REG_OFS	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IPU_CM_IC_REG_OFS	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IPU_CM_IRT_REG_OFS	0x00028000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IPU_CM_CSI0_REG_OFS	0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IPU_CM_CSI1_REG_OFS	0x00038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IPU_CM_SMFC_REG_OFS	0x00050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IPU_CM_DC_REG_OFS	0x00058000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IPU_CM_DMFC_REG_OFS	0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* IPU Common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IPU_CM_REG(offset)	(offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IPU_CONF			IPU_CM_REG(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IPU_SRM_PRI1			IPU_CM_REG(0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IPU_SRM_PRI2			IPU_CM_REG(0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IPU_FS_PROC_FLOW1		IPU_CM_REG(0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IPU_FS_PROC_FLOW2		IPU_CM_REG(0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IPU_FS_PROC_FLOW3		IPU_CM_REG(0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IPU_FS_DISP_FLOW1		IPU_CM_REG(0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IPU_FS_DISP_FLOW2		IPU_CM_REG(0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IPU_SKIP			IPU_CM_REG(0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IPU_DISP_ALT_CONF		IPU_CM_REG(0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IPU_DISP_GEN			IPU_CM_REG(0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IPU_DISP_ALT1			IPU_CM_REG(0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IPU_DISP_ALT2			IPU_CM_REG(0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IPU_DISP_ALT3			IPU_CM_REG(0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IPU_DISP_ALT4			IPU_CM_REG(0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IPU_SNOOP			IPU_CM_REG(0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IPU_MEM_RST			IPU_CM_REG(0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IPU_PM				IPU_CM_REG(0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IPU_GPR				IPU_CM_REG(0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IPU_CHA_DB_MODE_SEL(ch)		IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IPU_ALT_CHA_DB_MODE_SEL(ch)	IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IPU_CHA_CUR_BUF(ch)		IPU_CM_REG(0x023C + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IPU_ALT_CUR_BUF0		IPU_CM_REG(0x0244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IPU_ALT_CUR_BUF1		IPU_CM_REG(0x0248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IPU_SRM_STAT			IPU_CM_REG(0x024C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IPU_PROC_TASK_STAT		IPU_CM_REG(0x0250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IPU_DISP_TASK_STAT		IPU_CM_REG(0x0254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IPU_CHA_BUF0_RDY(ch)		IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IPU_CHA_BUF1_RDY(ch)		IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IPU_CHA_BUF2_RDY(ch)		IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IPU_ALT_CHA_BUF0_RDY(ch)	IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IPU_ALT_CHA_BUF1_RDY(ch)	IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IPU_INT_CTRL(n)		IPU_CM_REG(0x003C + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IPU_INT_STAT(n)		IPU_CM_REG(0x0200 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* SRM_PRI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DP_S_SRM_MODE_MASK		(0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DP_S_SRM_MODE_NOW		(0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DP_S_SRM_MODE_NEXT_FRAME	(0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* FS_PROC_FLOW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define FS_PRPENC_ROT_SRC_SEL_MASK	(0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define FS_PRPENC_ROT_SRC_SEL_ENC		(0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define FS_PRPVF_ROT_SRC_SEL_MASK	(0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define FS_PRPVF_ROT_SRC_SEL_VF			(0x8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define FS_PP_SRC_SEL_MASK		(0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define FS_PP_ROT_SRC_SEL_MASK		(0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define FS_PP_ROT_SRC_SEL_PP			(0x5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define FS_VDI1_SRC_SEL_MASK		(0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define FS_VDI3_SRC_SEL_MASK		(0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define FS_PRP_SRC_SEL_MASK		(0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define FS_VDI_SRC_SEL_MASK		(0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define FS_VDI_SRC_SEL_CSI_DIRECT		(0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define FS_VDI_SRC_SEL_VDOA			(0x2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* FS_PROC_FLOW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define FS_PRP_ENC_DEST_SEL_MASK	(0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define FS_PRP_ENC_DEST_SEL_IRT_ENC		(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define FS_PRPVF_DEST_SEL_MASK		(0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define FS_PRPVF_DEST_SEL_IRT_VF		(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define FS_PRPVF_ROT_DEST_SEL_MASK	(0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define FS_PP_DEST_SEL_MASK		(0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define FS_PP_DEST_SEL_IRT_PP			(0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define FS_PP_ROT_DEST_SEL_MASK		(0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define FS_PRPENC_ROT_DEST_SEL_MASK	(0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define FS_PRP_DEST_SEL_MASK		(0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IPU_DI0_COUNTER_RELEASE			(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IPU_DI1_COUNTER_RELEASE			(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IPU_IDMAC_REG(offset)	(offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IDMAC_CONF			IPU_IDMAC_REG(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IDMAC_CHA_EN(ch)		IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IDMAC_SEP_ALPHA			IPU_IDMAC_REG(0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IDMAC_ALT_SEP_ALPHA		IPU_IDMAC_REG(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IDMAC_CHA_PRI(ch)		IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IDMAC_WM_EN(ch)			IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IDMAC_CH_LOCK_EN_1		IPU_IDMAC_REG(0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IDMAC_CH_LOCK_EN_2		IPU_IDMAC_REG(0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IDMAC_SUB_ADDR_0		IPU_IDMAC_REG(0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IDMAC_SUB_ADDR_1		IPU_IDMAC_REG(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IDMAC_SUB_ADDR_2		IPU_IDMAC_REG(0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IDMAC_BAND_EN(ch)		IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IDMAC_CHA_BUSY(ch)		IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IPU_NUM_IRQS	(32 * 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum ipu_modules {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	IPU_CONF_CSI0_EN		= (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	IPU_CONF_CSI1_EN		= (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	IPU_CONF_IC_EN			= (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	IPU_CONF_ROT_EN			= (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	IPU_CONF_ISP_EN			= (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	IPU_CONF_DP_EN			= (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	IPU_CONF_DI0_EN			= (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	IPU_CONF_DI1_EN			= (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	IPU_CONF_SMFC_EN		= (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	IPU_CONF_DC_EN			= (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	IPU_CONF_DMFC_EN		= (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	IPU_CONF_VDI_EN			= (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	IPU_CONF_IDMAC_DIS		= (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	IPU_CONF_IC_DMFC_SEL		= (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	IPU_CONF_IC_DMFC_SYNC		= (1 << 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	IPU_CONF_VDI_DMFC_SYNC		= (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	IPU_CONF_CSI0_DATA_SOURCE	= (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	IPU_CONF_CSI1_DATA_SOURCE	= (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	IPU_CONF_IC_INPUT		= (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	IPU_CONF_CSI_SEL		= (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct ipuv3_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct ipu_soc *ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct ipu_cpmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ipu_csi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct ipu_dc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct ipu_dmfc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct ipu_di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct ipu_ic_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct ipu_vdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct ipu_image_convert_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ipu_smfc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct ipu_pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct ipu_prg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ipu_devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct ipu_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	const struct ipu_devtype	*devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	enum ipuv3_type		ipu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct mutex		channel_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct list_head	channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	void __iomem		*cm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	void __iomem		*idmac_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int			id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int			usecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int			irq_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int			irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct irq_domain	*domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct ipu_cpmem	*cpmem_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct ipu_dc_priv	*dc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct ipu_dp_priv	*dp_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct ipu_dmfc_priv	*dmfc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct ipu_di		*di_priv[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct ipu_csi		*csi_priv[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct ipu_ic_priv	*ic_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct ipu_vdi          *vdi_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct ipu_image_convert_priv *image_convert_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct ipu_smfc_priv	*smfc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct ipu_prg		*prg_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return readl(ipu->idmac_reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				   unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	writel(value, ipu->idmac_reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		 unsigned long base, u32 module, struct clk *clk_ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void ipu_csi_exit(struct ipu_soc *ipu, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		unsigned long base, unsigned long tpmem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void ipu_ic_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		 unsigned long base, u32 module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void ipu_vdi_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void ipu_image_convert_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		unsigned long base, u32 module, struct clk *ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void ipu_di_exit(struct ipu_soc *ipu, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		struct clk *ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void ipu_dmfc_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void ipu_dp_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		unsigned long template_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void ipu_dc_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void ipu_cpmem_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void ipu_smfc_exit(struct ipu_soc *ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 					  int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ipu_pre_get_available_count(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ipu_pre_get(struct ipu_pre *pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void ipu_pre_put(struct ipu_pre *pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 ipu_pre_get_baddr(struct ipu_pre *pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		       unsigned int height, unsigned int stride, u32 format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		       uint64_t modifier, unsigned int bufaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) bool ipu_pre_update_pending(struct ipu_pre *pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					  int ipu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) extern struct platform_driver ipu_pre_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) extern struct platform_driver ipu_prg_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif				/* __IPU_PRV_H__ */