^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2017 Lucas Stach, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ipu-prv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IPU_PRG_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IPU_PRG_CTL_BYPASS(i) (1 << (0 + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IPU_PRG_CTL_SOFT_ARID_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IPU_PRG_CTL_SOFT_ARID_SHIFT(i) (8 + i * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IPU_PRG_CTL_SOFT_ARID(i, v) ((v & 0x3) << (8 + 2 * i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IPU_PRG_CTL_SO(i) (1 << (16 + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPU_PRG_CTL_VFLIP(i) (1 << (19 + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IPU_PRG_CTL_BLOCK_MODE(i) (1 << (22 + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IPU_PRG_CTL_CNT_LOAD_EN(i) (1 << (25 + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IPU_PRG_CTL_SOFTRST (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IPU_PRG_CTL_SHADOW_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IPU_PRG_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IPU_PRG_STATUS_BUFFER0_READY(i) (1 << (0 + i * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IPU_PRG_STATUS_BUFFER1_READY(i) (1 << (1 + i * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IPU_PRG_QOS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IPU_PRG_QOS_ARID_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IPU_PRG_QOS_ARID_SHIFT(i) (0 + i * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IPU_PRG_REG_UPDATE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IPU_PRG_REG_UPDATE_REG_UPDATE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IPU_PRG_STRIDE(i) (0x10 + i * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IPU_PRG_STRIDE_STRIDE_MASK 0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IPU_PRG_CROP_LINE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IPU_PRG_THD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IPU_PRG_BADDR(i) (0x24 + i * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IPU_PRG_OFFSET(i) (0x30 + i * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IPU_PRG_ILO(i) (0x3c + i * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IPU_PRG_HEIGHT(i) (0x48 + i * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IPU_PRG_HEIGHT_PRE_HEIGHT_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IPU_PRG_HEIGHT_IPU_HEIGHT_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct ipu_prg_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int used_pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ipu_prg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *clk_ipg, *clk_axi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct regmap *iomuxc_gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct ipu_pre *pres[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ipu_prg_channel chan[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static DEFINE_MUTEX(ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static LIST_HEAD(ipu_prg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ipu_prg *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device_node *prg_node = of_parse_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ipu_prg *prg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mutex_lock(&ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) list_for_each_entry(prg, &ipu_prg_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (prg_node == prg->dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mutex_unlock(&ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) device_link_add(dev, prg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DL_FLAG_AUTOREMOVE_CONSUMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) prg->id = ipu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) of_node_put(prg_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return prg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mutex_unlock(&ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) of_node_put(prg_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ipu_prg_max_active_channels(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ipu_pre_get_available_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EXPORT_SYMBOL_GPL(ipu_prg_max_active_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool ipu_prg_present(struct ipu_soc *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ipu->prg_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EXPORT_SYMBOL_GPL(ipu_prg_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint64_t modifier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct drm_format_info *info = drm_format_info(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (info->num_planes != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) switch (modifier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case DRM_FORMAT_MOD_LINEAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case DRM_FORMAT_MOD_VIVANTE_TILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EXPORT_SYMBOL_GPL(ipu_prg_format_supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ipu_prg_enable(struct ipu_soc *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ipu_prg *prg = ipu->prg_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!prg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return pm_runtime_get_sync(prg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) EXPORT_SYMBOL_GPL(ipu_prg_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void ipu_prg_disable(struct ipu_soc *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ipu_prg *prg = ipu->prg_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!prg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pm_runtime_put(prg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) EXPORT_SYMBOL_GPL(ipu_prg_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * The channel configuartion functions below are not thread safe, as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * must be only called from the atomic commit path in the DRM driver, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * is properly serialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ipu_prg_ipu_to_prg_chan(int ipu_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * This isn't clearly documented in the RM, but IPU to PRG channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * assignment is fixed, as only with this mapping the control signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * match up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) switch (ipu_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case IPUV3_CHANNEL_MEM_BG_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case IPUV3_CHANNEL_MEM_FG_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case IPUV3_CHANNEL_MEM_DC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int ipu_prg_get_pre(struct ipu_prg *prg, int prg_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* channel 0 is special as it is hardwired to one of the PREs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (prg_chan == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = ipu_pre_get(prg->pres[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) prg->chan[prg_chan].used_pre = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (i = 1; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = ipu_pre_get(prg->pres[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 val, mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) prg->chan[prg_chan].used_pre = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* configure the PRE to PRG channel mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) shift = (i == 1) ? 12 : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mux = (prg->id << 1) | (prg_chan - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0x3 << shift, mux << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* check other mux, must not point to same channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) shift = (i == 1) ? 14 : 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) regmap_read(prg->iomuxc_gpr, IOMUXC_GPR5, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (((val >> shift) & 0x3) == mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) regmap_update_bits(prg->iomuxc_gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0x3 << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (mux ^ 0x1) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(prg->dev, "could not get PRE for PRG chan %d", prg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void ipu_prg_put_pre(struct ipu_prg *prg, int prg_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct ipu_prg_channel *chan = &prg->chan[prg_chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ipu_pre_put(prg->pres[chan->used_pre]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) chan->used_pre = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ipu_prg_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (prg_chan < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) chan = &prg->chan[prg_chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!chan->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pm_runtime_get_sync(prg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val = readl(prg->regs + IPU_PRG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val |= IPU_PRG_CTL_BYPASS(prg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(val, prg->regs + IPU_PRG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val = IPU_PRG_REG_UPDATE_REG_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(val, prg->regs + IPU_PRG_REG_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pm_runtime_put(prg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ipu_prg_put_pre(prg, prg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) chan->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) EXPORT_SYMBOL_GPL(ipu_prg_channel_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int axi_id, unsigned int width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int height, unsigned int stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 format, uint64_t modifier, unsigned long *eba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct ipu_prg_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (prg_chan < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return prg_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) chan = &prg->chan[prg_chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (chan->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ipu_pre_update(prg->pres[chan->used_pre], *eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = ipu_prg_get_pre(prg, prg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ipu_pre_configure(prg->pres[chan->used_pre],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) width, height, stride, format, modifier, *eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pm_runtime_get_sync(prg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = (stride - 1) & IPU_PRG_STRIDE_STRIDE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val = ((height & IPU_PRG_HEIGHT_PRE_HEIGHT_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ((height & IPU_PRG_HEIGHT_IPU_HEIGHT_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val = ipu_pre_get_baddr(prg->pres[chan->used_pre]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *eba = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val = readl(prg->regs + IPU_PRG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* config AXI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) val |= IPU_PRG_CTL_SOFT_ARID(prg_chan, axi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val &= ~IPU_PRG_CTL_BYPASS(prg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) writel(val, prg->regs + IPU_PRG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val = IPU_PRG_REG_UPDATE_REG_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) writel(val, prg->regs + IPU_PRG_REG_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* wait for both double buffers to be filled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) (val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 5, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pm_runtime_put(prg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) chan->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EXPORT_SYMBOL_GPL(ipu_prg_channel_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int prg_chan = ipu_prg_ipu_to_prg_chan(ipu_chan->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct ipu_prg *prg = ipu_chan->ipu->prg_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct ipu_prg_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (prg_chan < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) chan = &prg->chan[prg_chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) WARN_ON(!chan->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ipu_pre_update_pending(prg->pres[chan->used_pre]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) EXPORT_SYMBOL_GPL(ipu_prg_channel_configure_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int ipu_prg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct ipu_prg *prg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) prg = devm_kzalloc(dev, sizeof(*prg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!prg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) prg->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (IS_ERR(prg->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return PTR_ERR(prg->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) prg->clk_ipg = devm_clk_get(dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (IS_ERR(prg->clk_ipg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return PTR_ERR(prg->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) prg->clk_axi = devm_clk_get(dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (IS_ERR(prg->clk_axi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return PTR_ERR(prg->clk_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) prg->iomuxc_gpr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (IS_ERR(prg->iomuxc_gpr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return PTR_ERR(prg->iomuxc_gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) prg->pres[i] = ipu_pre_lookup_by_phandle(dev, "fsl,pres", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!prg->pres[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = clk_prepare_enable(prg->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = clk_prepare_enable(prg->clk_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) clk_disable_unprepare(prg->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* init to free running mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val = readl(prg->regs + IPU_PRG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val |= IPU_PRG_CTL_SHADOW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel(val, prg->regs + IPU_PRG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* disable address threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel(0xffffffff, prg->regs + IPU_PRG_THD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) prg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) platform_set_drvdata(pdev, prg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mutex_lock(&ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) list_add(&prg->list, &ipu_prg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mutex_unlock(&ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int ipu_prg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct ipu_prg *prg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mutex_lock(&ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) list_del(&prg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mutex_unlock(&ipu_prg_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int prg_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct ipu_prg *prg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk_disable_unprepare(prg->clk_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk_disable_unprepare(prg->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int prg_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct ipu_prg *prg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = clk_prepare_enable(prg->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = clk_prepare_enable(prg->clk_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clk_disable_unprepare(prg->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const struct dev_pm_ops prg_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SET_RUNTIME_PM_OPS(prg_suspend, prg_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const struct of_device_id ipu_prg_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { .compatible = "fsl,imx6qp-prg", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct platform_driver ipu_prg_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .probe = ipu_prg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .remove = ipu_prg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "imx-ipu-prg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .pm = &prg_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .of_match_table = ipu_prg_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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