Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017 Lucas Stach, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/genalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "ipu-prv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IPU_PRE_MAX_WIDTH	2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IPU_PRE_NUM_SCANLINES	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IPU_PRE_CTRL					0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IPU_PRE_CTRL_SET				0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define  IPU_PRE_CTRL_ENABLE				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define  IPU_PRE_CTRL_BLOCK_EN				(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define  IPU_PRE_CTRL_BLOCK_16				(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define  IPU_PRE_CTRL_SDW_UPDATE			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define  IPU_PRE_CTRL_VFLIP				(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  IPU_PRE_CTRL_SO				(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  IPU_PRE_CTRL_INTERLACED_FIELD			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define  IPU_PRE_CTRL_HANDSHAKE_EN			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define  IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v)		((v & 0x3) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define  IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define  IPU_PRE_CTRL_EN_REPEAT				(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define  IPU_PRE_CTRL_TPR_REST_SEL			(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define  IPU_PRE_CTRL_CLKGATE				(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define  IPU_PRE_CTRL_SFTRST				(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IPU_PRE_CUR_BUF					0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IPU_PRE_NEXT_BUF				0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IPU_PRE_TPR_CTRL				0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define  IPU_PRE_TPR_CTRL_TILE_FORMAT(v)		((v & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IPU_PRE_PREFETCH_ENG_CTRL			0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define  IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define  IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v)		((v & 0x7) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define  IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v)	((v & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define  IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v)	((v & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define  IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define  IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define  IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define  IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE			0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v)	((v & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v)	((v & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IPU_PRE_PREFETCH_ENG_PITCH			0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define  IPU_PRE_PREFETCH_ENG_PITCH_Y(v)		((v & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define  IPU_PRE_PREFETCH_ENG_PITCH_UV(v)		((v & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IPU_PRE_STORE_ENG_CTRL				0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define  IPU_PRE_STORE_ENG_CTRL_STORE_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define  IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v)		((v & 0x7) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define  IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v)	((v & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IPU_PRE_STORE_ENG_STATUS			0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK	0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL	(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIELD		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IPU_PRE_STORE_ENG_SIZE				0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define  IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v)		((v & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v)		((v & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IPU_PRE_STORE_ENG_PITCH				0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define  IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v)		((v & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IPU_PRE_STORE_ENG_ADDR				0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct ipu_pre {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct list_head	list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	void __iomem		*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct clk		*clk_axi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct gen_pool		*iram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dma_addr_t		buffer_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	void			*buffer_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	bool			in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned int		safe_window_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int		last_bufaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static DEFINE_MUTEX(ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static LIST_HEAD(ipu_pre_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int available_pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int ipu_pre_get_available_count(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return available_pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ipu_pre *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct device_node *pre_node = of_parse_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 							name, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct ipu_pre *pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	mutex_lock(&ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	list_for_each_entry(pre, &ipu_pre_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (pre_node == pre->dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			mutex_unlock(&ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			device_link_add(dev, pre->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					DL_FLAG_AUTOREMOVE_CONSUMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			of_node_put(pre_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			return pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mutex_unlock(&ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	of_node_put(pre_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ipu_pre_get(struct ipu_pre *pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (pre->in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* first get the engine out of reset and remove clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	writel(0, pre->regs + IPU_PRE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* init defaults that should be applied to all streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	      IPU_PRE_CTRL_HANDSHAKE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	      IPU_PRE_CTRL_TPR_REST_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	      IPU_PRE_CTRL_SDW_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	writel(val, pre->regs + IPU_PRE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	pre->in_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void ipu_pre_put(struct ipu_pre *pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	pre->in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		       unsigned int height, unsigned int stride, u32 format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		       uint64_t modifier, unsigned int bufaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	const struct drm_format_info *info = drm_format_info(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 active_bpp = info->cpp[0] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* calculate safe window for ctrl register updates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (modifier == DRM_FORMAT_MOD_LINEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		pre->safe_window_end = height - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	pre->last_bufaddr = bufaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	      IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	      IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	      IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	      IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	      IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	      IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	      IPU_PRE_STORE_ENG_CTRL_STORE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	      IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	val = readl(pre->regs + IPU_PRE_TPR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (modifier != DRM_FORMAT_MOD_LINEAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		/* only support single buffer formats for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (info->cpp[0] == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	writel(val, pre->regs + IPU_PRE_TPR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	val = readl(pre->regs + IPU_PRE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	       IPU_PRE_CTRL_SDW_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (modifier == DRM_FORMAT_MOD_LINEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		val &= ~IPU_PRE_CTRL_BLOCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		val |= IPU_PRE_CTRL_BLOCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	writel(val, pre->regs + IPU_PRE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	unsigned long timeout = jiffies + msecs_to_jiffies(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	unsigned short current_yblock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (bufaddr == pre->last_bufaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	pre->last_bufaddr = bufaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		current_yblock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			(val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	} while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bool ipu_pre_update_pending(struct ipu_pre *pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		  IPU_PRE_CTRL_SDW_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 ipu_pre_get_baddr(struct ipu_pre *pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return (u32)pre->buffer_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int ipu_pre_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct ipu_pre *pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	pre->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (IS_ERR(pre->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return PTR_ERR(pre->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	pre->clk_axi = devm_clk_get(dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (IS_ERR(pre->clk_axi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return PTR_ERR(pre->clk_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (!pre->iram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * Allocate IRAM buffer with maximum size. This could be made dynamic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * but as there is no other user of this IRAM region and we can fit all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * max sized buffers into it, there is no need yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 					      IPU_PRE_NUM_SCANLINES * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 					      &pre->buffer_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!pre->buffer_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	clk_prepare_enable(pre->clk_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	pre->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	platform_set_drvdata(pdev, pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	mutex_lock(&ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	list_add(&pre->list, &ipu_pre_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	available_pres++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	mutex_unlock(&ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int ipu_pre_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct ipu_pre *pre = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	mutex_lock(&ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	list_del(&pre->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	available_pres--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	mutex_unlock(&ipu_pre_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	clk_disable_unprepare(pre->clk_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (pre->buffer_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			      IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct of_device_id ipu_pre_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ .compatible = "fsl,imx6qp-pre", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct platform_driver ipu_pre_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.probe		= ipu_pre_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.remove		= ipu_pre_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.name	= "imx-ipu-pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.of_match_table = ipu_pre_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };