^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ipu-prv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct ipu_di {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk *clk_di; /* display input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *clk_ipu; /* IPU bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *clk_di_pixel; /* resulting pixel clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) bool inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct ipu_soc *ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static DEFINE_MUTEX(di_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct di_sync_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int run_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int run_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int offset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int offset_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int repeat_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int cnt_clr_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int cnt_polarity_gen_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int cnt_polarity_clr_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int cnt_polarity_trigger_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int cnt_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int cnt_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum di_pins {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DI_PIN11 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DI_PIN12 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DI_PIN13 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DI_PIN14 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DI_PIN15 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DI_PIN16 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DI_PIN17 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DI_PIN_CS = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DI_PIN_SER_CLK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DI_PIN_SER_RS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum di_sync_wave {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DI_SYNC_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DI_SYNC_CLK = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DI_SYNC_INT_HSYNC = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DI_SYNC_HSYNC = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DI_SYNC_VSYNC = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DI_SYNC_DE = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DI_SYNC_CNT1 = 2, /* counter >= 2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DI_SYNC_CNT4 = 5, /* counter >= 5 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DI_SYNC_CNT5 = 6, /* counter >= 6 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SYNC_WAVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DI_GENERAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DI_BS_CLKGEN0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DI_BS_CLKGEN1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DI_SYNC_AS_GEN 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DI_DW_GEN(gen) (0x0058 + 4 * (gen))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DI_SER_CONF 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DI_SSC 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DI_POL 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DI_AW0 0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DI_AW1 0x016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DI_SCR_CONF 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DI_STAT 0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DI_SW_GEN0_RUN_COUNT(x) ((x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DI_SW_GEN0_RUN_SRC(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DI_SW_GEN0_OFFSET_SRC(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DI_SW_GEN1_CNT_POL_GEN_EN(x) ((x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DI_SW_GEN1_CNT_CLR_SRC(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DI_SW_GEN1_CNT_POL_CLR_SRC(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DI_SW_GEN1_CNT_DOWN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DI_SW_GEN1_CNT_UP(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DI_SW_GEN1_AUTO_RELOAD (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DI_DW_GEN_ACCESS_SIZE_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DI_DW_GEN_COMPONENT_SIZE_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DI_GEN_POLARITY_1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DI_GEN_POLARITY_2 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DI_GEN_POLARITY_3 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DI_GEN_POLARITY_4 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DI_GEN_POLARITY_5 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DI_GEN_POLARITY_6 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DI_GEN_POLARITY_7 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DI_GEN_POLARITY_8 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DI_GEN_POLARITY_DISP_CLK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DI_GEN_DI_CLK_EXT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DI_GEN_DI_VSYNC_EXT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DI_POL_DRDY_DATA_POLARITY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DI_POL_DRDY_POLARITY_15 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DI_VSYNC_SEL_OFFSET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return readl(di->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(value, di->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void ipu_di_data_wave_config(struct ipu_di *di,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int wave_gen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int access_size, int component_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int set, int up, int down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg = ipu_di_read(di, DI_DW_GEN(wave_gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg &= ~(0x3 << (di_pin * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg |= set << (di_pin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int start, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct di_sync_config *c = &config[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int wave_gen = start + i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (c->repeat_count >= 0x1000) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (c->cnt_up >= 0x400) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (c->cnt_down >= 0x400)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(di->ipu->dev, "DI%d counters out of range.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) di->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg = DI_SW_GEN0_RUN_COUNT(c->run_count) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DI_SW_GEN0_RUN_SRC(c->run_src) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DI_SW_GEN0_OFFSET_COUNT(c->offset_count) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DI_SW_GEN0_OFFSET_SRC(c->offset_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ipu_di_write(di, reg, DI_SW_GEN0(wave_gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DI_SW_GEN1_CNT_POL_TRIGGER_SRC(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) c->cnt_polarity_trigger_src) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DI_SW_GEN1_CNT_DOWN(c->cnt_down) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DI_SW_GEN1_CNT_UP(c->cnt_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Enable auto reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (c->repeat_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg |= DI_SW_GEN1_AUTO_RELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ipu_di_write(di, reg, DI_SW_GEN1(wave_gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reg = ipu_di_read(di, DI_STP_REP(wave_gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ipu_di_write(di, reg, DI_STP_REP(wave_gen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void ipu_di_sync_config_interlaced(struct ipu_di *di,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct ipu_di_signal_cfg *sig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sig->mode.hback_porch + sig->mode.hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) sig->mode.vback_porch + sig->mode.vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct di_sync_config cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* 1: internal VSYNC for each frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .run_count = v_total * 2 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .run_src = 3, /* == counter 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* PIN2: HSYNC waveform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .run_count = h_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cnt_polarity_trigger_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .cnt_down = sig->mode.hsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* PIN3: VSYNC waveform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .run_count = v_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .run_src = 4, /* == counter 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .cnt_polarity_trigger_src = 4, /* == counter 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .cnt_down = sig->mode.vsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .cnt_clr_src = DI_SYNC_CNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* 4: Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .run_count = v_total / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .run_src = DI_SYNC_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .offset_count = h_total / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .offset_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .repeat_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .cnt_clr_src = DI_SYNC_CNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* 5: Active lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .run_src = DI_SYNC_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .offset_count = (sig->mode.vsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) sig->mode.vback_porch) / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .offset_src = DI_SYNC_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .repeat_count = sig->mode.vactive / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .cnt_clr_src = DI_SYNC_CNT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* 6: Active pixel, referenced by DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .offset_count = sig->mode.hsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) sig->mode.hback_porch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .offset_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .repeat_count = sig->mode.hactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .cnt_clr_src = DI_SYNC_CNT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* 7: Half line HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .run_count = h_total / 2 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct ipu_di_signal_cfg *sig, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sig->mode.hback_porch + sig->mode.hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) sig->mode.vback_porch + sig->mode.vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct di_sync_config cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* 1: INT_HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .run_count = h_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* PIN2: HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .run_count = h_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .offset_count = div * sig->v_to_h_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .offset_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .cnt_polarity_trigger_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .cnt_down = sig->mode.hsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* PIN3: VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .run_count = v_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .run_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .cnt_down = sig->mode.vsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* 4: Line Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .run_src = DI_SYNC_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .offset_count = sig->mode.vsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sig->mode.vback_porch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .offset_src = DI_SYNC_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .repeat_count = sig->mode.vactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .cnt_clr_src = DI_SYNC_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* 5: Pixel Active, referenced by DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .offset_count = sig->mode.hsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) sig->mode.hback_porch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .offset_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .repeat_count = sig->mode.hactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .cnt_clr_src = 5, /* Line Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* can't use #7 and #8 for line active and pixel active counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct di_sync_config cfg_vga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* 1: INT_HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .run_count = h_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* 2: VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .run_count = v_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .run_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* 3: Line Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .run_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .offset_count = sig->mode.vsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) sig->mode.vback_porch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .offset_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .repeat_count = sig->mode.vactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .cnt_clr_src = 3 /* VSYNC */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .run_count = h_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .offset_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .cnt_polarity_trigger_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .cnt_down = sig->mode.hsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* 5: Pixel Active signal to DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .offset_count = sig->mode.hsync_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) sig->mode.hback_porch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .offset_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .repeat_count = sig->mode.hactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .cnt_clr_src = 4, /* Line Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .run_count = v_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .run_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .offset_count = 1, /* magic value from Freescale TVE driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .offset_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .cnt_down = sig->mode.vsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .run_count = h_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .run_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .offset_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .cnt_polarity_trigger_src = DI_SYNC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .cnt_down = sig->mode.hsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .run_count = v_total - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .run_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .offset_count = 1, /* magic value from Freescale TVE driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .offset_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .cnt_polarity_gen_en = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .cnt_down = sig->mode.vsync_len * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } , {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ipu_di_write(di, v_total - 1, DI_SCR_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (sig->hsync_pin == 2 && sig->vsync_pin == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void ipu_di_config_clock(struct ipu_di *di,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) const struct ipu_di_signal_cfg *sig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned clkgen0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * CLKMODE_EXT means we must use the DI clock: this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * needed for things like LVDS which needs to feed the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * DI and LDB with the same pixel clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clk = di->clk_di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (sig->clkflags & IPU_DI_CLKMODE_SYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * CLKMODE_SYNC means that we want the DI to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * clocked at the same rate as the parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * This is needed (eg) for LDB which needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * fed with the same pixel clock. We assume that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * the LDB clock has already been set correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clkgen0 = 1 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * We can use the divider. We should really have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * a flag here indicating whether the bridge can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * cope with a fractional divider or not. For the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * time being, let's go for simplicitly and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * reliability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned long in_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_set_rate(clk, sig->mode.pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) in_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) div = clamp(div, 1U, 255U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clkgen0 = div << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * For other interfaces, we can arbitarily select between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * the DI specific clock and the internal IPU clock. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * DI_GENERAL bit 20. We select the IPU clock if it can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * give us a clock rate within 1% of the requested frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * otherwise we use the DI clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long rate, clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned div, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clkrate = clk_get_rate(di->clk_ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) div = clamp(div, 1U, 255U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rate = clkrate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) error = rate / (sig->mode.pixelclock / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) rate, div, (signed)(error - 1000) / 10, error % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Allow a 1% error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (error < 1010 && error >= 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) clk = di->clk_ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) clkgen0 = div << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long in_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) clk = di->clk_di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) clk_set_rate(clk, sig->mode.pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) in_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) div = clamp(div, 1U, 255U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) clkgen0 = div << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) di->clk_di_pixel = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Set the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ipu_di_write(di, clkgen0, DI_BS_CLKGEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * Set the high/low periods. Bits 24:16 give us the falling edge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * and bits 8:0 give the rising edge. LSB is fraction, and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * based on the divider above. We want a 50% duty cycle, so set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * the falling edge to be half the divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Finally select the input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (clk == di->clk_di)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) val |= DI_GEN_DI_CLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ipu_di_write(di, val, DI_GENERAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) sig->mode.pixelclock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clk_get_rate(di->clk_ipu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk_get_rate(di->clk_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) clk == di->clk_di ? "DI" : "IPU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * This function is called to adjust a video mode to IPU restrictions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * It is meant to be called from drm crtc mode_fixup() methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (mode->vfront_porch >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) diff = 2 - mode->vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (mode->vback_porch >= diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mode->vfront_porch = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mode->vback_porch -= diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } else if (mode->vsync_len > diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mode->vfront_porch = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mode->vsync_len = mode->vsync_len - diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_warn(di->ipu->dev, "failed to adjust videomode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_dbg(di->ipu->dev, "videomode adapted for IPU restrictions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) EXPORT_SYMBOL_GPL(ipu_di_adjust_videomode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static u32 ipu_di_gen_polarity(int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) switch (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return DI_GEN_POLARITY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return DI_GEN_POLARITY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return DI_GEN_POLARITY_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return DI_GEN_POLARITY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return DI_GEN_POLARITY_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return DI_GEN_POLARITY_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return DI_GEN_POLARITY_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return DI_GEN_POLARITY_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 di_gen, vsync_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) di->id, sig->mode.hactive, sig->mode.vactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clk_get_rate(di->clk_ipu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) clk_get_rate(di->clk_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sig->mode.pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mutex_lock(&di_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ipu_di_config_clock(di, sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) div = div / 16; /* Now divider is integer portion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Setup pixel clock timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Down time is half of period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ipu_di_write(di, (div << 16), DI_BS_CLKGEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) di_gen |= DI_GEN_DI_VSYNC_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ipu_di_sync_config_interlaced(di, sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* set y_sel = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) di_gen |= 0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) vsync_cnt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ipu_di_sync_config_noninterlaced(di, sig, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) vsync_cnt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (di->id == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * TODO: change only for TVEv2, parallel display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * uses pin 2 / 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vsync_cnt = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) di_gen |= ipu_di_gen_polarity(sig->hsync_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) di_gen |= ipu_di_gen_polarity(sig->vsync_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (sig->clk_pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) di_gen |= DI_GEN_POLARITY_DISP_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ipu_di_write(di, di_gen, DI_GENERAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) DI_SYNC_AS_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) reg = ipu_di_read(di, DI_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (sig->enable_pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reg |= DI_POL_DRDY_POLARITY_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (sig->data_pol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) reg |= DI_POL_DRDY_DATA_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ipu_di_write(di, reg, DI_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) mutex_unlock(&di_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int ipu_di_enable(struct ipu_di *di)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) WARN_ON(IS_ERR(di->clk_di_pixel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret = clk_prepare_enable(di->clk_di_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ipu_module_enable(di->ipu, di->module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) EXPORT_SYMBOL_GPL(ipu_di_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int ipu_di_disable(struct ipu_di *di)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) WARN_ON(IS_ERR(di->clk_di_pixel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ipu_module_disable(di->ipu, di->module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) clk_disable_unprepare(di->clk_di_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) EXPORT_SYMBOL_GPL(ipu_di_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ipu_di_get_num(struct ipu_di *di)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return di->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) EXPORT_SYMBOL_GPL(ipu_di_get_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static DEFINE_MUTEX(ipu_di_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct ipu_di *di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (disp > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) di = ipu->di_priv[disp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mutex_lock(&ipu_di_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (di->inuse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) di = ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) di->inuse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mutex_unlock(&ipu_di_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) EXPORT_SYMBOL_GPL(ipu_di_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) void ipu_di_put(struct ipu_di *di)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mutex_lock(&ipu_di_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) di->inuse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) mutex_unlock(&ipu_di_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) EXPORT_SYMBOL_GPL(ipu_di_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned long base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 module, struct clk *clk_ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct ipu_di *di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (id > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!di)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ipu->di_priv[id] = di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) di->clk_di = devm_clk_get(dev, id ? "di1" : "di0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (IS_ERR(di->clk_di))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return PTR_ERR(di->clk_di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) di->module = module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) di->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) di->clk_ipu = clk_ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) di->base = devm_ioremap(dev, base, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!di->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ipu_di_write(di, 0x10, DI_BS_CLKGEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) id, base, di->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) di->inuse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) di->ipu = ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) void ipu_di_exit(struct ipu_soc *ipu, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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