^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ipu-prv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DC_EVT_NF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DC_EVT_NL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DC_EVT_EOF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DC_EVT_NFIELD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DC_EVT_EOL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DC_EVT_EOFIELD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DC_EVT_NEW_ADDR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DC_EVT_NEW_CHAN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DC_EVT_NEW_DATA 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DC_EVT_NEW_ADDR_W_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DC_EVT_NEW_ADDR_W_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DC_EVT_NEW_CHAN_W_0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DC_EVT_NEW_CHAN_W_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DC_EVT_NEW_DATA_W_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DC_EVT_NEW_DATA_W_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DC_EVT_NEW_ADDR_R_0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DC_EVT_NEW_ADDR_R_1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DC_EVT_NEW_CHAN_R_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DC_EVT_NEW_CHAN_R_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DC_EVT_NEW_DATA_R_0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DC_EVT_NEW_DATA_R_1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DC_WR_CH_CONF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DC_WR_CH_ADDR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DC_GEN 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DC_STAT 0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WROD(lf) (0x18 | ((lf) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WRG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WCLK 0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SYNC_WAVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NULL_WAVE (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DC_GEN_SYNC_1_6_SYNC (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IPU_DC_NUM_CHANNELS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ipu_dc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum ipu_dc_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) IPU_DC_MAP_RGB24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) IPU_DC_MAP_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) IPU_DC_MAP_GBR24, /* TVEv2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) IPU_DC_MAP_BGR666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) IPU_DC_MAP_LVDS666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) IPU_DC_MAP_BGR24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ipu_dc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* The display interface number assigned to this dc channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ipu_dc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int chno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct ipu_dc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __iomem *dc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __iomem *dc_tmpl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ipu_soc *ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int use_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg = readl(dc->base + DC_RL_CH(event));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg &= ~(0xffff << (16 * (event & 0x1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(reg, dc->base + DC_RL_CH(event));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int map, int wave, int glue, int sync, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct ipu_dc_priv *priv = dc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 reg1, reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (opcode == WCLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg1 = (operand << 20) & 0xfff00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg2 = operand >> 12 | opcode << 1 | stop << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else if (opcode == WRG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg2 = operand >> 17 | opcode << 7 | stop << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg2 = operand >> 12 | opcode << 4 | stop << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(reg1, priv->dc_tmpl_reg + word * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int ipu_bus_format_to_map(u32 fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case MEDIA_BUS_FMT_RGB888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return IPU_DC_MAP_RGB24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case MEDIA_BUS_FMT_RGB565_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return IPU_DC_MAP_RGB565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case MEDIA_BUS_FMT_GBR888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return IPU_DC_MAP_GBR24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case MEDIA_BUS_FMT_RGB666_1X18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return IPU_DC_MAP_BGR666;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return IPU_DC_MAP_LVDS666;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case MEDIA_BUS_FMT_BGR888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return IPU_DC_MAP_BGR24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 bus_format, u32 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ipu_dc_priv *priv = dc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int addr, sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dc->di = ipu_di_get_num(di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) map = ipu_bus_format_to_map(bus_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * In interlaced mode we need more counters to create the asymmetric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * per-field VSYNC signals. The pixel active signal synchronising DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * to DI moves to signal generator #6 (see ipu-di.c). In progressive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * mode counter #5 is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sync = interlaced ? 6 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Reserve 5 microcode template words for each DI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (dc->di)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) addr = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (interlaced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dc_link_event(dc, DC_EVT_NL, addr, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dc_link_event(dc, DC_EVT_EOL, addr, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Init template microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Init template microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dc_link_event(dc, DC_EVT_NF, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dc_link_event(dc, DC_EVT_EOF, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reg = readl(dc->base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg |= DC_WR_CH_CONF_FIELD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg &= ~DC_WR_CH_CONF_FIELD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(reg, dc->base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(0x0, dc->base + DC_WR_CH_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void ipu_dc_enable(struct ipu_soc *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct ipu_dc_priv *priv = ipu->dc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mutex_lock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!priv->use_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) priv->use_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EXPORT_SYMBOL_GPL(ipu_dc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void ipu_dc_enable_channel(struct ipu_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg = readl(dc->base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(reg, dc->base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void ipu_dc_disable_channel(struct ipu_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val = readl(dc->base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(val, dc->base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void ipu_dc_disable(struct ipu_soc *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct ipu_dc_priv *priv = ipu->dc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mutex_lock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) priv->use_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!priv->use_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (priv->use_count < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) priv->use_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EXPORT_SYMBOL_GPL(ipu_dc_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int byte_num, int offset, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ptr = map * 3 + byte_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) reg &= ~(0xffff << (16 * (ptr & 0x1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) writel(reg & ~(0xffff << (16 * (map & 0x1))),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) priv->dc_reg + DC_MAP_CONF_PTR(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct ipu_dc_priv *priv = ipu->dc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct ipu_dc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (channel >= IPU_DC_NUM_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dc = &priv->channels[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mutex_lock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (dc->in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dc->in_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) EXPORT_SYMBOL_GPL(ipu_dc_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void ipu_dc_put(struct ipu_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct ipu_dc_priv *priv = dc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_lock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dc->in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) EXPORT_SYMBOL_GPL(ipu_dc_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long base, unsigned long template_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct ipu_dc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x78, 0, 0x94, 0xb4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mutex_init(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) priv->ipu = ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!priv->dc_reg || !priv->dc_tmpl_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) priv->channels[i].chno = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) priv->channels[i].priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->channels[i].base = priv->dc_reg + channel_offsets[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DC_WR_CH_CONF_PROG_DI_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) priv->channels[1].base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) priv->channels[5].base + DC_WR_CH_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->dc_reg + DC_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ipu->dc_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) base, template_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* rgb24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* rgb565 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* gbr24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* bgr666 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* lvds666 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* bgr24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void ipu_dc_exit(struct ipu_soc *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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