^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2013 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission to use, copy, modify, distribute, and sell this software and its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * documentation for any purpose is hereby granted without fee, provided that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the above copyright notice appear in all copies and that both that copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * notice and this permission notice appear in supporting documentation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * that the name of the copyright holders not be used in advertising or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * publicity pertaining to distribution of the software without specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * written prior permission. The copyright holders make no representations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * about the suitability of this software for any purpose. It is provided "as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * is" without express or implied warranty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OF THIS SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/host1x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MIPI_CAL_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MIPI_CAL_CTRL_START (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIPI_CAL_AUTOCAL_CTRL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIPI_CAL_STATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIPI_CAL_STATUS_DONE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MIPI_CAL_STATUS_ACTIVE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MIPI_CAL_CONFIG_CSIA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MIPI_CAL_CONFIG_CSIB 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MIPI_CAL_CONFIG_CSIC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MIPI_CAL_CONFIG_CSID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MIPI_CAL_CONFIG_CSIE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MIPI_CAL_CONFIG_CSIF 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MIPI_CAL_CONFIG_DSIA 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MIPI_CAL_CONFIG_DSIB 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MIPI_CAL_CONFIG_DSIC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MIPI_CAL_CONFIG_DSID 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MIPI_CAL_CONFIG_DSIA_CLK 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MIPI_CAL_CONFIG_DSIB_CLK 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MIPI_CAL_CONFIG_DSIC_CLK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MIPI_CAL_CONFIG_DSID_CLK 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* for data and clock lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MIPI_CAL_CONFIG_SELECT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* for data lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* for clock lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MIPI_CAL_BIAS_PAD_CFG0 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MIPI_CAL_BIAS_PAD_CFG1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MIPI_CAL_BIAS_PAD_CFG2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct tegra_mipi_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct tegra_mipi_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool has_clk_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct tegra_mipi_pad *pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int num_pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool clock_enable_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool needs_vclamp_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* bias pad configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 pad_drive_down_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 pad_drive_up_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 pad_vclamp_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 pad_vauxp_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* calibration settings for data lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 hspdos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 hspuos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 termos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* calibration settings for clock lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 hsclkpdos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 hsclkpuos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct tegra_mipi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct tegra_mipi_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long usage_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct tegra_mipi_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct tegra_mipi *mipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return readl(mipi->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(value, mipi->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int tegra_mipi_power_up(struct tegra_mipi *mipi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) err = clk_enable(mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (mipi->soc->needs_vclamp_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clk_disable(mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int tegra_mipi_power_down(struct tegra_mipi *mipi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) err = clk_enable(mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * The MIPI_CAL_BIAS_PAD_PDVREG controls a voltage regulator that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * supplies the DSI pads. This must be kept enabled until none of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * DSI lanes are used anymore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) value |= MIPI_CAL_BIAS_PAD_PDVREG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * MIPI_CAL_BIAS_PAD_PDVCLAMP and MIPI_CAL_BIAS_PAD_E_VCLAMP_REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * control a regulator that supplies current to the pre-driver logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Powering down this regulator causes DSI to fail, so it must remain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * powered on until none of the DSI lanes are used anymore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (mipi->soc->needs_vclamp_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) value &= ~MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct tegra_mipi_device *tegra_mipi_request(struct device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct tegra_mipi_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "#nvidia,mipi-calibrate-cells", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev->pdev = of_find_device_by_node(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!dev->pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev->mipi = platform_get_drvdata(dev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!dev->mipi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev->pads = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev->device = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) platform_device_put(dev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXPORT_SYMBOL(tegra_mipi_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void tegra_mipi_free(struct tegra_mipi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) platform_device_put(device->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) kfree(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EXPORT_SYMBOL(tegra_mipi_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int tegra_mipi_enable(struct tegra_mipi_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mutex_lock(&dev->mipi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (dev->mipi->usage_count++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err = tegra_mipi_power_up(dev->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mutex_unlock(&dev->mipi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXPORT_SYMBOL(tegra_mipi_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int tegra_mipi_disable(struct tegra_mipi_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mutex_lock(&dev->mipi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (--dev->mipi->usage_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) err = tegra_mipi_power_down(dev->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mutex_unlock(&dev->mipi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) EXPORT_SYMBOL(tegra_mipi_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int tegra_mipi_finish_calibration(struct tegra_mipi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct tegra_mipi *mipi = device->mipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void __iomem *status_reg = mipi->regs + (MIPI_CAL_STATUS << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) err = readl_relaxed_poll_timeout(status_reg, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) !(value & MIPI_CAL_STATUS_ACTIVE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) (value & MIPI_CAL_STATUS_DONE), 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 250000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mutex_unlock(&device->mipi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clk_disable(device->mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) EXPORT_SYMBOL(tegra_mipi_finish_calibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const struct tegra_mipi_soc *soc = device->mipi->soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) err = clk_enable(device->mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mutex_lock(&device->mipi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) for (i = 0; i < soc->num_pads; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 clk = 0, data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (device->pads & BIT(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) data = MIPI_CAL_CONFIG_SELECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MIPI_CAL_CONFIG_TERMOS(soc->termos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clk = MIPI_CAL_CONFIG_SELECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (soc->has_clk_lane && soc->pads[i].clk != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) value |= MIPI_CAL_CTRL_PRESCALE(0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!soc->clock_enable_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) value |= MIPI_CAL_CTRL_CLKEN_OVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* clear any pending status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) value |= MIPI_CAL_CTRL_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Wait for min 72uS to let calibration logic finish calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * sequence codes before waiting for pads idle state to apply the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) usleep_range(75, 80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) EXPORT_SYMBOL(tegra_mipi_start_calibration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .data = MIPI_CAL_CONFIG_CSIA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .data = MIPI_CAL_CONFIG_CSIB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { .data = MIPI_CAL_CONFIG_CSIC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { .data = MIPI_CAL_CONFIG_CSID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { .data = MIPI_CAL_CONFIG_CSIE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { .data = MIPI_CAL_CONFIG_DSIA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { .data = MIPI_CAL_CONFIG_DSIB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { .data = MIPI_CAL_CONFIG_DSIC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { .data = MIPI_CAL_CONFIG_DSID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct tegra_mipi_soc tegra114_mipi_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .has_clk_lane = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .pads = tegra114_mipi_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .num_pads = ARRAY_SIZE(tegra114_mipi_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .clock_enable_override = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .needs_vclamp_ref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .pad_drive_down_ref = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .pad_drive_up_ref = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .pad_vclamp_level = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pad_vauxp_level = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .hspdos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .hspuos = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .termos = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .hsclkpdos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .hsclkpuos = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct tegra_mipi_soc tegra124_mipi_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .has_clk_lane = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .pads = tegra124_mipi_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .clock_enable_override = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .needs_vclamp_ref = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .pad_drive_down_ref = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .pad_drive_up_ref = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pad_vclamp_level = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .pad_vauxp_level = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .hspdos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .hspuos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .termos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .hsclkpdos = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .hsclkpuos = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct tegra_mipi_soc tegra132_mipi_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .has_clk_lane = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .pads = tegra124_mipi_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .clock_enable_override = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .needs_vclamp_ref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .pad_drive_down_ref = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .pad_drive_up_ref = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .pad_vclamp_level = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .pad_vauxp_level = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .hspdos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .hspuos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .termos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .hsclkpdos = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .hsclkpuos = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct tegra_mipi_pad tegra210_mipi_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { .data = MIPI_CAL_CONFIG_CSIA, .clk = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { .data = MIPI_CAL_CONFIG_CSIB, .clk = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { .data = MIPI_CAL_CONFIG_CSIC, .clk = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { .data = MIPI_CAL_CONFIG_CSID, .clk = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { .data = MIPI_CAL_CONFIG_CSIE, .clk = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { .data = MIPI_CAL_CONFIG_CSIF, .clk = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { .data = MIPI_CAL_CONFIG_DSIC, .clk = MIPI_CAL_CONFIG_DSIC_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { .data = MIPI_CAL_CONFIG_DSID, .clk = MIPI_CAL_CONFIG_DSID_CLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct tegra_mipi_soc tegra210_mipi_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .has_clk_lane = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .pads = tegra210_mipi_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .num_pads = ARRAY_SIZE(tegra210_mipi_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .clock_enable_override = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .needs_vclamp_ref = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .pad_drive_down_ref = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .pad_drive_up_ref = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .pad_vclamp_level = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .pad_vauxp_level = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .hspdos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .hspuos = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .termos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .hsclkpdos = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .hsclkpuos = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct of_device_id tegra_mipi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { .compatible = "nvidia,tegra132-mipi", .data = &tegra132_mipi_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { .compatible = "nvidia,tegra210-mipi", .data = &tegra210_mipi_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int tegra_mipi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct tegra_mipi *mipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!mipi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mipi->soc = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mipi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mipi->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (IS_ERR(mipi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return PTR_ERR(mipi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mutex_init(&mipi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mipi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (IS_ERR(mipi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return PTR_ERR(mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) err = clk_prepare(mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) platform_set_drvdata(pdev, mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int tegra_mipi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct tegra_mipi *mipi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) clk_unprepare(mipi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct platform_driver tegra_mipi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .name = "tegra-mipi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .of_match_table = tegra_mipi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .probe = tegra_mipi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .remove = tegra_mipi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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