^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) config DRM_ZYNQMP_DPSUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) tristate "ZynqMP DisplayPort Controller Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) depends on ARCH_ZYNQMP || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) depends on COMMON_CLK && DRM && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) depends on DMADEVICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) select DRM_GEM_CMA_HELPER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) select DRM_KMS_CMA_HELPER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) select DRM_KMS_HELPER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) select GENERIC_PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) this option if you have a Xilinx ZynqMP SoC with DisplayPort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) subsystem.