Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRM driver for display panels connected to a Sitronix ST7715R or ST7735R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * display controller in SPI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2017 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2019 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dma-buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <drm/drm_mipi_dbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ST7735R_FRMCTR1		0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ST7735R_FRMCTR2		0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ST7735R_FRMCTR3		0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ST7735R_INVCTR		0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ST7735R_PWCTR1		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ST7735R_PWCTR2		0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ST7735R_PWCTR3		0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ST7735R_PWCTR4		0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ST7735R_PWCTR5		0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ST7735R_VMCTR1		0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ST7735R_GAMCTRP1	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ST7735R_GAMCTRN1	0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ST7735R_MY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ST7735R_MX	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ST7735R_MV	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ST7735R_RGB	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) struct st7735r_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	const struct drm_display_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int left_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int top_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int write_only:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int rgb:1;		/* RGB (vs. BGR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct st7735r_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct mipi_dbi_dev dbidev;	/* Must be first for .release() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	const struct st7735r_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static void st7735r_pipe_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct st7735r_priv *priv = container_of(dbidev, struct st7735r_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 						 dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct mipi_dbi *dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u8 addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	DRM_DEBUG_KMS("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ret = mipi_dbi_poweron_reset(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mipi_dbi_command(dbi, ST7735R_FRMCTR1, 0x01, 0x2c, 0x2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mipi_dbi_command(dbi, ST7735R_FRMCTR2, 0x01, 0x2c, 0x2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mipi_dbi_command(dbi, ST7735R_FRMCTR3, 0x01, 0x2c, 0x2d, 0x01, 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			 0x2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mipi_dbi_command(dbi, ST7735R_INVCTR, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	mipi_dbi_command(dbi, ST7735R_PWCTR1, 0xa2, 0x02, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	mipi_dbi_command(dbi, ST7735R_PWCTR2, 0xc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mipi_dbi_command(dbi, ST7735R_PWCTR3, 0x0a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	mipi_dbi_command(dbi, ST7735R_PWCTR4, 0x8a, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mipi_dbi_command(dbi, ST7735R_PWCTR5, 0x8a, 0xee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	mipi_dbi_command(dbi, ST7735R_VMCTR1, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	switch (dbidev->rotation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		addr_mode = ST7735R_MX | ST7735R_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		addr_mode = ST7735R_MX | ST7735R_MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		addr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		addr_mode = ST7735R_MY | ST7735R_MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (priv->cfg->rgb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		addr_mode |= ST7735R_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			 MIPI_DCS_PIXEL_FMT_16BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	mipi_dbi_command(dbi, ST7735R_GAMCTRP1, 0x02, 0x1c, 0x07, 0x12, 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			 0x32, 0x29, 0x2d, 0x29, 0x25, 0x2b, 0x39, 0x00, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			 0x03, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	mipi_dbi_command(dbi, ST7735R_GAMCTRN1, 0x03, 0x1d, 0x07, 0x06, 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			 0x2c, 0x29, 0x2d, 0x2e, 0x2e, 0x37, 0x3f, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			 0x02, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	mipi_dbi_command(dbi, MIPI_DCS_ENTER_NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct drm_simple_display_pipe_funcs st7735r_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.enable		= st7735r_pipe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.disable	= mipi_dbi_pipe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.update		= mipi_dbi_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct st7735r_cfg jd_t18003_t01_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.mode		= { DRM_SIMPLE_MODE(128, 160, 28, 35) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* Cannot read from Adafruit 1.8" display via SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.write_only	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct st7735r_cfg rh128128t_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.mode		= { DRM_SIMPLE_MODE(128, 128, 25, 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.left_offset	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.top_offset	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.rgb		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEFINE_DRM_GEM_CMA_FOPS(st7735r_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct drm_driver st7735r_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.fops			= &st7735r_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.debugfs_init		= mipi_dbi_debugfs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.name			= "st7735r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.desc			= "Sitronix ST7735R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.date			= "20171128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.major			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.minor			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct of_device_id st7735r_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ .compatible = "jianda,jd-t18003-t01", .data = &jd_t18003_t01_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ .compatible = "okaya,rh128128t", .data = &rh128128t_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_DEVICE_TABLE(of, st7735r_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct spi_device_id st7735r_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ "jd-t18003-t01", (uintptr_t)&jd_t18003_t01_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_DEVICE_TABLE(spi, st7735r_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int st7735r_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	const struct st7735r_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct mipi_dbi_dev *dbidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct st7735r_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct mipi_dbi *dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct gpio_desc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 rotation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	cfg = device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		cfg = (void *)spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	priv = devm_drm_dev_alloc(dev, &st7735r_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				  struct st7735r_priv, dbidev.drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (IS_ERR(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return PTR_ERR(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	dbidev = &priv->dbidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	priv->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	drm = &dbidev->drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (IS_ERR(dbi->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return PTR_ERR(dbi->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (IS_ERR(dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return PTR_ERR(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	dbidev->backlight = devm_of_find_backlight(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (IS_ERR(dbidev->backlight))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return PTR_ERR(dbidev->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	device_property_read_u32(dev, "rotation", &rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ret = mipi_dbi_spi_init(spi, dbi, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (cfg->write_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		dbi->read_commands = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	dbidev->left_offset = cfg->left_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	dbidev->top_offset = cfg->top_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ret = mipi_dbi_dev_init(dbidev, &st7735r_pipe_funcs, &cfg->mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	drm_mode_config_reset(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = drm_dev_register(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	spi_set_drvdata(spi, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	drm_fbdev_generic_setup(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int st7735r_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct drm_device *drm = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	drm_dev_unplug(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	drm_atomic_helper_shutdown(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void st7735r_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct spi_driver st7735r_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.name = "st7735r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.of_match_table = st7735r_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.id_table = st7735r_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.probe = st7735r_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.remove = st7735r_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.shutdown = st7735r_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_spi_driver(st7735r_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_DESCRIPTION("Sitronix ST7735R DRM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_AUTHOR("David Lechner <david@lechnology.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL");