Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRM driver for Sitronix ST7586 panels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2017 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/dma-buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <drm/drm_damage_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_fb_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_format_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <drm/drm_mipi_dbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <drm/drm_rect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* controller-specific commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ST7586_DISP_MODE_GRAY	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ST7586_DISP_MODE_MONO	0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ST7586_ENABLE_DDRAM	0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ST7586_SET_DISP_DUTY	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ST7586_SET_PART_DISP	0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ST7586_SET_NLINE_INV	0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ST7586_SET_VOP		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ST7586_SET_BIAS_SYSTEM	0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ST7586_SET_BOOST_LEVEL	0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ST7586_SET_VOP_OFFSET	0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ST7586_ENABLE_ANALOG	0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ST7586_AUTO_READ_CTRL	0xd7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ST7586_OTP_RW_CTRL	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ST7586_OTP_CTRL_OUT	0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ST7586_OTP_READ		0xe3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ST7586_DISP_CTRL_MX	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ST7586_DISP_CTRL_MY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * The ST7586 controller has an unusual pixel format where 2bpp grayscale is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * packed 3 pixels per byte with the first two pixels using 3 bits and the 3rd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * pixel using only 2 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * |  D7  |  D6  |  D5  ||      |      || 2bpp |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * | (D4) | (D3) | (D2) ||  D1  |  D0  || GRAY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * +------+------+------++------+------++------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * |  1   |  1   |  1   ||  1   |  1   || 0  0 | black
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * |  1   |  0   |  0   ||  1   |  0   || 0  1 | dark gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * |  0   |  1   |  0   ||  0   |  1   || 1  0 | light gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * |  0   |  0   |  0   ||  0   |  0   || 1  1 | white
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const u8 st7586_lookup[] = { 0x7, 0x4, 0x2, 0x0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void st7586_xrgb8888_to_gray332(u8 *dst, void *vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				       struct drm_framebuffer *fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				       struct drm_rect *clip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	size_t len = (clip->x2 - clip->x1) * (clip->y2 - clip->y1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 *src, *buf, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	buf = kmalloc(len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	drm_fb_xrgb8888_to_gray8(buf, vaddr, fb, clip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	src = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	for (y = clip->y1; y < clip->y2; y++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		for (x = clip->x1; x < clip->x2; x += 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			val = st7586_lookup[*src++ >> 6] << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			val |= st7586_lookup[*src++ >> 6] << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			val |= st7586_lookup[*src++ >> 6] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			*dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int st7586_buf_copy(void *dst, struct drm_framebuffer *fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			   struct drm_rect *clip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	void *src = cma_obj->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (import_attach) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					       DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	st7586_xrgb8888_to_gray332(dst, src, fb, clip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (import_attach)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 					     DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void st7586_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct mipi_dbi *dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int start, end, idx, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (!drm_dev_enter(fb->dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* 3 pixels per byte, so grow clip to nearest multiple of 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	rect->x1 = rounddown(rect->x1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	rect->x2 = roundup(rect->x2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ret = st7586_buf_copy(dbidev->tx_buf, fb, rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		goto err_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Pixels are packed 3 per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	start = rect->x1 / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	end = rect->x2 / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			 (start >> 8) & 0xFF, start & 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			 (end >> 8) & 0xFF, (end - 1) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			 (rect->y1 >> 8) & 0xFF, rect->y1 & 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			 (rect->y2 >> 8) & 0xFF, (rect->y2 - 1) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				   (u8 *)dbidev->tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				   (end - start) * (rect->y2 - rect->y1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) err_msg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void st7586_pipe_update(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			       struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct drm_plane_state *state = pipe->plane.state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct drm_rect rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (!pipe->crtc.state->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		st7586_fb_dirty(state->fb, &rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			       struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			       struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct drm_framebuffer *fb = plane_state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct mipi_dbi *dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct drm_rect rect = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.x1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.x2 = fb->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.y1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.y2 = fb->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u8 addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	DRM_DEBUG_KMS("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ret = mipi_dbi_poweron_reset(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	mipi_dbi_command(dbi, ST7586_AUTO_READ_CTRL, 0x9f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	mipi_dbi_command(dbi, ST7586_OTP_RW_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mipi_dbi_command(dbi, ST7586_OTP_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mipi_dbi_command(dbi, ST7586_OTP_CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mipi_dbi_command(dbi, ST7586_SET_VOP_OFFSET, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	mipi_dbi_command(dbi, ST7586_SET_VOP, 0xe3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	mipi_dbi_command(dbi, ST7586_SET_BIAS_SYSTEM, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	mipi_dbi_command(dbi, ST7586_SET_BOOST_LEVEL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mipi_dbi_command(dbi, ST7586_ENABLE_ANALOG, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mipi_dbi_command(dbi, ST7586_SET_NLINE_INV, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	mipi_dbi_command(dbi, ST7586_DISP_MODE_GRAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	mipi_dbi_command(dbi, ST7586_ENABLE_DDRAM, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	switch (dbidev->rotation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		addr_mode = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		addr_mode = ST7586_DISP_CTRL_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		addr_mode = ST7586_DISP_CTRL_MX | ST7586_DISP_CTRL_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		addr_mode = ST7586_DISP_CTRL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	mipi_dbi_command(dbi, ST7586_SET_DISP_DUTY, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	mipi_dbi_command(dbi, ST7586_SET_PART_DISP, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_ROWS, 0x00, 0x00, 0x00, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	st7586_fb_dirty(fb, &rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void st7586_pipe_disable(struct drm_simple_display_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * This callback is not protected by drm_dev_enter/exit since we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 * turn off the display on regular driver unload. It's highly unlikely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * that the underlying SPI controller is gone should this be called after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * unplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	DRM_DEBUG_KMS("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	mipi_dbi_command(&dbidev->dbi, MIPI_DCS_SET_DISPLAY_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const u32 st7586_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	DRM_FORMAT_XRGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct drm_simple_display_pipe_funcs st7586_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.enable		= st7586_pipe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.disable	= st7586_pipe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.update		= st7586_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct drm_display_mode st7586_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	DRM_SIMPLE_MODE(178, 128, 37, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DEFINE_DRM_GEM_CMA_FOPS(st7586_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct drm_driver st7586_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.fops			= &st7586_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.debugfs_init		= mipi_dbi_debugfs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.name			= "st7586",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.desc			= "Sitronix ST7586",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.date			= "20170801",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.major			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.minor			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct of_device_id st7586_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ .compatible = "lego,ev3-lcd" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_DEVICE_TABLE(of, st7586_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct spi_device_id st7586_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{ "ev3-lcd", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DEVICE_TABLE(spi, st7586_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int st7586_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct mipi_dbi_dev *dbidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct mipi_dbi *dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct gpio_desc *a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u32 rotation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	size_t bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	dbidev = devm_drm_dev_alloc(dev, &st7586_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				    struct mipi_dbi_dev, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (IS_ERR(dbidev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return PTR_ERR(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	drm = &dbidev->drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	bufsize = (st7586_mode.vdisplay + 2) / 3 * st7586_mode.hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (IS_ERR(dbi->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return PTR_ERR(dbi->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	a0 = devm_gpiod_get(dev, "a0", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (IS_ERR(a0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'a0'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return PTR_ERR(a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	device_property_read_u32(dev, "rotation", &rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	ret = mipi_dbi_spi_init(spi, dbi, a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	/* Cannot read from this controller via SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	dbi->read_commands = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ret = mipi_dbi_dev_init_with_formats(dbidev, &st7586_pipe_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 					     st7586_formats, ARRAY_SIZE(st7586_formats),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 					     &st7586_mode, rotation, bufsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	 * we are using 8-bit data, so we are not actually swapping anything,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 * but setting mipi->swap_bytes makes mipi_dbi_typec3_command() do the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	 * right thing and not use 16-bit transfers (which results in swapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	 * bytes on little-endian systems and causes out of order data to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	 * sent to the display).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	dbi->swap_bytes = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	drm_mode_config_reset(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	ret = drm_dev_register(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	spi_set_drvdata(spi, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	drm_fbdev_generic_setup(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int st7586_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct drm_device *drm = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	drm_dev_unplug(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	drm_atomic_helper_shutdown(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void st7586_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct spi_driver st7586_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.name = "st7586",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		.of_match_table = st7586_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.id_table = st7586_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.probe = st7586_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.remove = st7586_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.shutdown = st7586_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) module_spi_driver(st7586_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_DESCRIPTION("Sitronix ST7586 DRM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_AUTHOR("David Lechner <david@lechnology.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_LICENSE("GPL");