^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRM driver for Pervasive Displays RePaper branded e-ink panels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013-2017 Pervasive Displays, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2017 Noralf Trønnes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The driver supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Material Film: Aurora Mb (V231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Driver IC: G2 (eTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The controller code was taken from the userspace driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * https://github.com/repaper/gratis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dma-buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_damage_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <drm/drm_fb_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <drm/drm_format_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <drm/drm_rect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REPAPER_RID_G2_COG_ID 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum repaper_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* 0 is reserved to avoid clashing with NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) E1144CS021 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) E1190CS021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) E2200CS021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) E2271CS021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum repaper_stage { /* Image pixel -> Display pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) REPAPER_COMPENSATE, /* B -> W, W -> B (Current Image) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) REPAPER_WHITE, /* B -> N, W -> W (Current Image) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) REPAPER_INVERSE, /* B -> N, W -> B (New Image) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) REPAPER_NORMAL /* B -> B, W -> W (New Image) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum repaper_epd_border_byte {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) REPAPER_BORDER_BYTE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) REPAPER_BORDER_BYTE_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) REPAPER_BORDER_BYTE_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct repaper_epd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct drm_device drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct drm_simple_display_pipe pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct gpio_desc *panel_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct gpio_desc *border;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct gpio_desc *discharge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct gpio_desc *busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct thermal_zone_device *thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int bytes_per_scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const u8 *channel_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int stage_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int factored_stage_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool middle_scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool pre_border_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum repaper_epd_border_byte border_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 *line_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void *current_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool cleared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bool partial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline struct repaper_epd *drm_to_epd(struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return container_of(drm, struct repaper_epd, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int repaper_spi_transfer(struct spi_device *spi, u8 header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const void *tx, void *rx, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void *txbuf = NULL, *rxbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct spi_transfer tr[2] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 *headerbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) headerbuf = kmalloc(1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!headerbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) headerbuf[0] = header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tr[0].tx_buf = headerbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tr[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Stack allocated tx? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (tx && len <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) txbuf = kmemdup(tx, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!txbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rxbuf = kmalloc(len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tr[1].tx_buf = txbuf ? txbuf : tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) tr[1].rx_buf = rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tr[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ndelay(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = spi_sync_transfer(spi, tr, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (rx && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) memcpy(rx, rxbuf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) kfree(headerbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) kfree(txbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) kfree(rxbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int repaper_write_buf(struct spi_device *spi, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const u8 *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = repaper_spi_transfer(spi, 0x70, ®, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return repaper_spi_transfer(spi, 0x72, buf, NULL, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int repaper_write_val(struct spi_device *spi, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return repaper_write_buf(spi, reg, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int repaper_read_val(struct spi_device *spi, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = repaper_spi_transfer(spi, 0x70, ®, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = repaper_spi_transfer(spi, 0x73, NULL, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret ? ret : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int repaper_read_id(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = repaper_spi_transfer(spi, 0x71, NULL, &id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret ? ret : id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void repaper_spi_mosi_low(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const u8 buf[1] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spi_write(spi, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* pixels on display are numbered from 1 so even is actually bits 1,3,5,... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void repaper_even_pixels(struct repaper_epd *epd, u8 **pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const u8 *data, u8 fixed_value, const u8 *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) for (b = 0; b < (epd->width / 8); b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 pixels = data[b] & 0xaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 pixel_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 p1, p2, p3, p4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pixel_mask = (mask[b] ^ pixels) & 0xaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pixel_mask |= pixel_mask >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) switch (stage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pixels = 0xaa | ((pixels ^ 0xaa) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case REPAPER_WHITE: /* B -> N, W -> W (Current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pixels = 0x55 + ((pixels ^ 0xaa) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case REPAPER_INVERSE: /* B -> N, W -> B (New) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pixels = 0x55 | (pixels ^ 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case REPAPER_NORMAL: /* B -> B, W -> W (New) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pixels = 0xaa | (pixels >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) p1 = (pixels >> 6) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) p2 = (pixels >> 4) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) p3 = (pixels >> 2) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) p4 = (pixels >> 0) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *(*pp)++ = pixels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *(*pp)++ = fixed_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* pixels on display are numbered from 1 so odd is actually bits 0,2,4,... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void repaper_odd_pixels(struct repaper_epd *epd, u8 **pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const u8 *data, u8 fixed_value, const u8 *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (b = epd->width / 8; b > 0; b--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 pixels = data[b - 1] & 0x55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 pixel_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pixel_mask = (mask[b - 1] ^ pixels) & 0x55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pixel_mask |= pixel_mask << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (stage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pixels = 0xaa | (pixels ^ 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case REPAPER_WHITE: /* B -> N, W -> W (Current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pixels = 0x55 + (pixels ^ 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case REPAPER_INVERSE: /* B -> N, W -> B (New) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pixels = 0x55 | ((pixels ^ 0x55) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case REPAPER_NORMAL: /* B -> B, W -> W (New) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pixels = 0xaa | pixels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *(*pp)++ = pixels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *(*pp)++ = fixed_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* interleave bits: (byte)76543210 -> (16 bit).7.6.5.4.3.2.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static inline u16 repaper_interleave_bits(u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) value = (value | (value << 4)) & 0x0f0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) value = (value | (value << 2)) & 0x3333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) value = (value | (value << 1)) & 0x5555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* pixels on display are numbered from 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void repaper_all_pixels(struct repaper_epd *epd, u8 **pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const u8 *data, u8 fixed_value, const u8 *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (b = epd->width / 8; b > 0; b--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u16 pixels = repaper_interleave_bits(data[b - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 pixel_mask = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pixel_mask = repaper_interleave_bits(mask[b - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pixel_mask = (pixel_mask ^ pixels) & 0x5555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pixel_mask |= pixel_mask << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) switch (stage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pixels = 0xaaaa | (pixels ^ 0x5555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case REPAPER_WHITE: /* B -> N, W -> W (Current) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pixels = 0x5555 + (pixels ^ 0x5555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case REPAPER_INVERSE: /* B -> N, W -> B (New) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pixels = 0x5555 | ((pixels ^ 0x5555) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case REPAPER_NORMAL: /* B -> B, W -> W (New) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pixels = 0xaaaa | pixels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pixels = (pixels & pixel_mask) | (~pixel_mask & 0x5555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *(*pp)++ = pixels >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *(*pp)++ = pixels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *(*pp)++ = fixed_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *(*pp)++ = fixed_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* output one line of scan and data bytes to the display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void repaper_one_line(struct repaper_epd *epd, unsigned int line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const u8 *data, u8 fixed_value, const u8 *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 *p = epd->line_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) repaper_spi_mosi_low(epd->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (epd->pre_border_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *p++ = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (epd->middle_scan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* data bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) repaper_odd_pixels(epd, &p, data, fixed_value, mask, stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* scan line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (b = epd->bytes_per_scan; b > 0; b--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (line / 4 == b - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *p++ = 0x03 << (2 * (line & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *p++ = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* data bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) repaper_even_pixels(epd, &p, data, fixed_value, mask, stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * even scan line, but as lines on display are numbered from 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * line: 1,3,5,...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (b = 0; b < epd->bytes_per_scan; b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (0 != (line & 0x01) && line / 8 == b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *p++ = 0xc0 >> (line & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *p++ = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* data bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) repaper_all_pixels(epd, &p, data, fixed_value, mask, stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * odd scan line, but as lines on display are numbered from 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * line: 0,2,4,6,...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) for (b = epd->bytes_per_scan; b > 0; b--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (0 == (line & 0x01) && line / 8 == b - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *p++ = 0x03 << (line & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *p++ = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (epd->border_byte) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case REPAPER_BORDER_BYTE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case REPAPER_BORDER_BYTE_ZERO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *p++ = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case REPAPER_BORDER_BYTE_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) switch (stage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case REPAPER_COMPENSATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case REPAPER_WHITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case REPAPER_INVERSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *p++ = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case REPAPER_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *p++ = 0xaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) repaper_write_buf(epd->spi, 0x0a, epd->line_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) p - epd->line_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Output data to panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) repaper_write_val(epd->spi, 0x02, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) repaper_spi_mosi_low(epd->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void repaper_frame_fixed(struct repaper_epd *epd, u8 fixed_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) for (line = 0; line < epd->height; line++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) repaper_one_line(epd, line, NULL, fixed_value, NULL, stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void repaper_frame_data(struct repaper_epd *epd, const u8 *image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) const u8 *mask, enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (line = 0; line < epd->height; line++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) repaper_one_line(epd, line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &image[line * (epd->width / 8)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0, NULL, stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for (line = 0; line < epd->height; line++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) size_t n = line * epd->width / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) repaper_one_line(epd, line, &image[n], 0, &mask[n],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void repaper_frame_fixed_repeat(struct repaper_epd *epd, u8 fixed_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u64 start = local_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u64 end = start + (epd->factored_stage_time * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) repaper_frame_fixed(epd, fixed_value, stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) } while (local_clock() < end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void repaper_frame_data_repeat(struct repaper_epd *epd, const u8 *image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) const u8 *mask, enum repaper_stage stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u64 start = local_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u64 end = start + (epd->factored_stage_time * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) repaper_frame_data(epd, image, mask, stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } while (local_clock() < end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void repaper_get_temperature(struct repaper_epd *epd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret, temperature = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int factor10x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!epd->thermal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = thermal_zone_get_temp(epd->thermal, &temperature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DRM_DEV_ERROR(&epd->spi->dev, "Failed to get temperature (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) temperature /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (temperature <= -10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) factor10x = 170;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else if (temperature <= -5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) factor10x = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) else if (temperature <= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) factor10x = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) else if (temperature <= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) factor10x = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) else if (temperature <= 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) factor10x = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) else if (temperature <= 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) factor10x = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) else if (temperature <= 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) factor10x = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) factor10x = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) epd->factored_stage_time = epd->stage_time * factor10x / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static void repaper_gray8_to_mono_reversed(u8 *buf, u32 width, u32 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 *gray8 = buf, *mono = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int y, xb, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (y = 0; y < height; y++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) for (xb = 0; xb < width / 8; xb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 byte = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int x = xb * 8 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) byte >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (gray8[y * width + x] >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) byte |= BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *mono++ = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int repaper_fb_dirty(struct drm_framebuffer *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct repaper_epd *epd = drm_to_epd(fb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct drm_rect clip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int idx, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 *buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!drm_dev_enter(fb->dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* repaper can't do partial updates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) clip.x1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) clip.x2 = fb->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) clip.y1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clip.y2 = fb->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) repaper_get_temperature(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DRM_DEBUG("Flushing [FB:%d] st=%ums\n", fb->base.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) epd->factored_stage_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) buf = kmalloc_array(fb->width, fb->height, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (import_attach) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) drm_fb_xrgb8888_to_gray8(buf, cma_obj->vaddr, fb, &clip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (import_attach) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = dma_buf_end_cpu_access(import_attach->dmabuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) repaper_gray8_to_mono_reversed(buf, fb->width, fb->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (epd->partial) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) repaper_frame_data_repeat(epd, buf, epd->current_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) REPAPER_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else if (epd->cleared) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) repaper_frame_data_repeat(epd, epd->current_frame, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) REPAPER_COMPENSATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) repaper_frame_data_repeat(epd, epd->current_frame, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) REPAPER_WHITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) epd->partial = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Clear display (anything -> white) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) repaper_frame_fixed_repeat(epd, 0xff, REPAPER_COMPENSATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) repaper_frame_fixed_repeat(epd, 0xff, REPAPER_WHITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_INVERSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Assuming a clear (white) screen output an image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_COMPENSATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_WHITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) epd->cleared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) epd->partial = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) memcpy(epd->current_frame, buf, fb->width * fb->height / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * An extra frame write is needed if pixels are set in the bottom line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * or else grey lines rises up from the pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (epd->pre_border_byte) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for (x = 0; x < (fb->width / 8); x++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (buf[x + (fb->width * (fb->height - 1) / 8)]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) repaper_frame_data_repeat(epd, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) epd->current_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) REPAPER_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void power_off(struct repaper_epd *epd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Turn off power and all signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) gpiod_set_value_cansleep(epd->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) gpiod_set_value_cansleep(epd->panel_on, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (epd->border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) gpiod_set_value_cansleep(epd->border, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Ensure SPI MOSI and CLOCK are Low before CS Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) repaper_spi_mosi_low(epd->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Discharge pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) gpiod_set_value_cansleep(epd->discharge, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) gpiod_set_value_cansleep(epd->discharge, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct spi_device *spi = epd->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bool dc_ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int i, ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!drm_dev_enter(pipe->crtc.dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) DRM_DEBUG_DRIVER("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Power up sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) gpiod_set_value_cansleep(epd->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) gpiod_set_value_cansleep(epd->panel_on, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) gpiod_set_value_cansleep(epd->discharge, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (epd->border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) gpiod_set_value_cansleep(epd->border, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) repaper_spi_mosi_low(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) gpiod_set_value_cansleep(epd->panel_on, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * This delay comes from the repaper.org userspace driver, it's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * mentioned in the datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) gpiod_set_value_cansleep(epd->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (epd->border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) gpiod_set_value_cansleep(epd->border, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) gpiod_set_value_cansleep(epd->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) gpiod_set_value_cansleep(epd->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Wait for COG to become ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for (i = 100; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (!gpiod_get_value_cansleep(epd->busy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) DRM_DEV_ERROR(dev, "timeout waiting for panel to become ready.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) power_off(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) repaper_read_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = repaper_read_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret != REPAPER_RID_G2_COG_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(dev, "failed to read chip (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_err(dev, "wrong COG ID 0x%02x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) power_off(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Disable OE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) repaper_write_val(spi, 0x02, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret = repaper_read_val(spi, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ret < 0 || !(ret & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) DRM_DEV_ERROR(dev, "panel is reported broken\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) power_off(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Power saving mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) repaper_write_val(spi, 0x0b, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Channel select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) repaper_write_buf(spi, 0x01, epd->channel_select, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* High power mode osc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) repaper_write_val(spi, 0x07, 0xd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Power setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) repaper_write_val(spi, 0x08, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Vcom level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) repaper_write_val(spi, 0x09, 0xc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Power setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) repaper_write_val(spi, 0x04, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Driver latch on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) repaper_write_val(spi, 0x03, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Driver latch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) repaper_write_val(spi, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Start chargepump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) for (i = 0; i < 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Charge pump positive voltage on - VGH/VDL on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) repaper_write_val(spi, 0x05, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) msleep(240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Charge pump negative voltage on - VGL/VDL on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) repaper_write_val(spi, 0x05, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Charge pump Vcom on - Vcom driver on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) repaper_write_val(spi, 0x05, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* check DC/DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = repaper_read_val(spi, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) power_off(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dc_ok = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!dc_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DRM_DEV_ERROR(dev, "dc/dc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) power_off(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Output enable to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * The userspace driver sets this to 0x04, but the datasheet says 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) repaper_write_val(spi, 0x02, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) epd->partial = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void repaper_pipe_disable(struct drm_simple_display_pipe *pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct spi_device *spi = epd->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * This callback is not protected by drm_dev_enter/exit since we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * turn off the display on regular driver unload. It's highly unlikely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * that the underlying SPI controller is gone should this be called after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * unplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) DRM_DEBUG_DRIVER("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Nothing frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) for (line = 0; line < epd->height; line++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) REPAPER_COMPENSATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* 2.7" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (epd->border) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Dummy line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) REPAPER_COMPENSATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) gpiod_set_value_cansleep(epd->border, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) gpiod_set_value_cansleep(epd->border, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Border dummy line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) REPAPER_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* not described in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) repaper_write_val(spi, 0x0b, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Latch reset turn on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) repaper_write_val(spi, 0x03, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Power off charge pump Vcom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) repaper_write_val(spi, 0x05, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Power off charge pump neg voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) repaper_write_val(spi, 0x05, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Discharge internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) repaper_write_val(spi, 0x04, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* turn off all charge pumps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) repaper_write_val(spi, 0x05, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Turn off osc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) repaper_write_val(spi, 0x07, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) power_off(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static void repaper_pipe_update(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct drm_plane_state *state = pipe->plane.state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct drm_rect rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!pipe->crtc.state->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (drm_atomic_helper_damage_merged(old_state, state, &rect))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) repaper_fb_dirty(state->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const struct drm_simple_display_pipe_funcs repaper_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .enable = repaper_pipe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .disable = repaper_pipe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .update = repaper_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int repaper_connector_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct repaper_epd *epd = drm_to_epd(connector->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) mode = drm_mode_duplicate(connector->dev, epd->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) DRM_ERROR("Failed to duplicate mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) drm_mode_set_name(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mode->type |= DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) connector->display_info.width_mm = mode->width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) connector->display_info.height_mm = mode->height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const struct drm_connector_helper_funcs repaper_connector_hfuncs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .get_modes = repaper_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const struct drm_connector_funcs repaper_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .destroy = drm_connector_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct drm_mode_config_funcs repaper_mode_config_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .fb_create = drm_gem_fb_create_with_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .atomic_check = drm_atomic_helper_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .atomic_commit = drm_atomic_helper_commit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const uint32_t repaper_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) DRM_FORMAT_XRGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const struct drm_display_mode repaper_e1144cs021_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) DRM_SIMPLE_MODE(128, 96, 29, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static const u8 repaper_e1144cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) 0x00, 0x0f, 0xff, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const struct drm_display_mode repaper_e1190cs021_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) DRM_SIMPLE_MODE(144, 128, 36, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const u8 repaper_e1190cs021_cs[] = { 0x00, 0x00, 0x00, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) 0xfc, 0x00, 0x00, 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const struct drm_display_mode repaper_e2200cs021_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) DRM_SIMPLE_MODE(200, 96, 46, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const u8 repaper_e2200cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) 0x01, 0xff, 0xe0, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const struct drm_display_mode repaper_e2271cs021_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) DRM_SIMPLE_MODE(264, 176, 57, 38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const u8 repaper_e2271cs021_cs[] = { 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) 0xff, 0xfe, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) DEFINE_DRM_GEM_CMA_FOPS(repaper_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static struct drm_driver repaper_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .fops = &repaper_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DRM_GEM_CMA_DRIVER_OPS_VMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .name = "repaper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .desc = "Pervasive Displays RePaper e-ink panels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .date = "20170405",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .major = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const struct of_device_id repaper_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { .compatible = "pervasive,e1144cs021", .data = (void *)E1144CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { .compatible = "pervasive,e1190cs021", .data = (void *)E1190CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { .compatible = "pervasive,e2200cs021", .data = (void *)E2200CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { .compatible = "pervasive,e2271cs021", .data = (void *)E2271CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) MODULE_DEVICE_TABLE(of, repaper_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const struct spi_device_id repaper_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { "e1144cs021", E1144CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) { "e1190cs021", E1190CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { "e2200cs021", E2200CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { "e2271cs021", E2271CS021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) MODULE_DEVICE_TABLE(spi, repaper_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int repaper_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) const struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) const struct spi_device_id *spi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) enum repaper_model model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) const char *thermal_zone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct repaper_epd *epd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) size_t line_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) const void *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) match = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) model = (enum repaper_model)match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) spi_id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) model = (enum repaper_model)spi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* The SPI device is used to allocate dma memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (!dev->coherent_dma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev_warn(dev, "Failed to set dma mask %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) epd = devm_drm_dev_alloc(dev, &repaper_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct repaper_epd, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (IS_ERR(epd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return PTR_ERR(epd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) drm = &epd->drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = drmm_mode_config_init(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) drm->mode_config.funcs = &repaper_mode_config_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) epd->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) epd->panel_on = devm_gpiod_get(dev, "panel-on", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (IS_ERR(epd->panel_on)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = PTR_ERR(epd->panel_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) DRM_DEV_ERROR(dev, "Failed to get gpio 'panel-on'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) epd->discharge = devm_gpiod_get(dev, "discharge", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (IS_ERR(epd->discharge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret = PTR_ERR(epd->discharge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) DRM_DEV_ERROR(dev, "Failed to get gpio 'discharge'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) epd->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (IS_ERR(epd->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = PTR_ERR(epd->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) epd->busy = devm_gpiod_get(dev, "busy", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (IS_ERR(epd->busy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = PTR_ERR(epd->busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) DRM_DEV_ERROR(dev, "Failed to get gpio 'busy'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!device_property_read_string(dev, "pervasive,thermal-zone",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) &thermal_zone)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) epd->thermal = thermal_zone_get_zone_by_name(thermal_zone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (IS_ERR(epd->thermal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) DRM_DEV_ERROR(dev, "Failed to get thermal zone: %s\n", thermal_zone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return PTR_ERR(epd->thermal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) switch (model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) case E1144CS021:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mode = &repaper_e1144cs021_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) epd->channel_select = repaper_e1144cs021_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) epd->stage_time = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) epd->bytes_per_scan = 96 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) epd->middle_scan = true; /* data-scan-data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) epd->pre_border_byte = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) epd->border_byte = REPAPER_BORDER_BYTE_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case E1190CS021:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) mode = &repaper_e1190cs021_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) epd->channel_select = repaper_e1190cs021_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) epd->stage_time = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) epd->bytes_per_scan = 128 / 4 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) epd->middle_scan = false; /* scan-data-scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) epd->pre_border_byte = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) epd->border_byte = REPAPER_BORDER_BYTE_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case E2200CS021:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mode = &repaper_e2200cs021_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) epd->channel_select = repaper_e2200cs021_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) epd->stage_time = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) epd->bytes_per_scan = 96 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) epd->middle_scan = true; /* data-scan-data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) epd->pre_border_byte = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) epd->border_byte = REPAPER_BORDER_BYTE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case E2271CS021:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) epd->border = devm_gpiod_get(dev, "border", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (IS_ERR(epd->border)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret = PTR_ERR(epd->border);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) DRM_DEV_ERROR(dev, "Failed to get gpio 'border'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mode = &repaper_e2271cs021_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) epd->channel_select = repaper_e2271cs021_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) epd->stage_time = 630;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) epd->bytes_per_scan = 176 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) epd->middle_scan = true; /* data-scan-data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) epd->pre_border_byte = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) epd->border_byte = REPAPER_BORDER_BYTE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) epd->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) epd->width = mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) epd->height = mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) epd->factored_stage_time = epd->stage_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) line_buffer_size = 2 * epd->width / 8 + epd->bytes_per_scan + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) epd->line_buffer = devm_kzalloc(dev, line_buffer_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (!epd->line_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) epd->current_frame = devm_kzalloc(dev, epd->width * epd->height / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (!epd->current_frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) drm->mode_config.min_width = mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) drm->mode_config.max_width = mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) drm->mode_config.min_height = mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) drm->mode_config.max_height = mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) drm_connector_helper_add(&epd->connector, &repaper_connector_hfuncs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = drm_connector_init(drm, &epd->connector, &repaper_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) DRM_MODE_CONNECTOR_SPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret = drm_simple_display_pipe_init(drm, &epd->pipe, &repaper_pipe_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) repaper_formats, ARRAY_SIZE(repaper_formats),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) NULL, &epd->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) drm_mode_config_reset(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ret = drm_dev_register(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) spi_set_drvdata(spi, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) drm_fbdev_generic_setup(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int repaper_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct drm_device *drm = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) drm_dev_unplug(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) drm_atomic_helper_shutdown(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static void repaper_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) drm_atomic_helper_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static struct spi_driver repaper_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .name = "repaper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .of_match_table = repaper_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .id_table = repaper_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .probe = repaper_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .remove = repaper_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .shutdown = repaper_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) module_spi_driver(repaper_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) MODULE_DESCRIPTION("Pervasive Displays RePaper DRM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) MODULE_AUTHOR("Noralf Trønnes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags