Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRM driver for Multi-Inno MI0283QT panels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2016 Noralf Trønnes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_mipi_dbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_modeset_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ILI9341_FRMCTR1		0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ILI9341_DISCTRL		0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ILI9341_ETMOD		0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ILI9341_PWCTRL1		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ILI9341_PWCTRL2		0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ILI9341_VMCTRL1		0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ILI9341_VMCTRL2		0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ILI9341_PWCTRLA		0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ILI9341_PWCTRLB		0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ILI9341_PGAMCTRL	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ILI9341_NGAMCTRL	0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ILI9341_DTCTRLA		0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ILI9341_DTCTRLB		0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ILI9341_PWRSEQ		0xed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ILI9341_EN3GAM		0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ILI9341_PUMPCTRL	0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ILI9341_MADCTL_BGR	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ILI9341_MADCTL_MV	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ILI9341_MADCTL_MX	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ILI9341_MADCTL_MY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void mi0283qt_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			    struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			    struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct mipi_dbi *dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8 addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	DRM_DEBUG_KMS("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ret = mipi_dbi_poweron_conditional_reset(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		goto out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mipi_dbi_command(dbi, ILI9341_PWCTRLB, 0x00, 0x83, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	mipi_dbi_command(dbi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	mipi_dbi_command(dbi, ILI9341_DTCTRLA, 0x85, 0x01, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mipi_dbi_command(dbi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	mipi_dbi_command(dbi, ILI9341_PUMPCTRL, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	mipi_dbi_command(dbi, ILI9341_DTCTRLB, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* Power Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mipi_dbi_command(dbi, ILI9341_PWCTRL1, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	mipi_dbi_command(dbi, ILI9341_PWCTRL2, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* VCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mipi_dbi_command(dbi, ILI9341_VMCTRL1, 0x35, 0x3e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mipi_dbi_command(dbi, ILI9341_VMCTRL2, 0xbe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* Memory Access Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* Frame Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	mipi_dbi_command(dbi, ILI9341_FRMCTR1, 0x00, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mipi_dbi_command(dbi, ILI9341_EN3GAM, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	mipi_dbi_command(dbi, ILI9341_PGAMCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		       0x1f, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		       0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	mipi_dbi_command(dbi, ILI9341_NGAMCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		       0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		       0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* DDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mipi_dbi_command(dbi, ILI9341_ETMOD, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* Display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	mipi_dbi_command(dbi, ILI9341_DISCTRL, 0x0a, 0x82, 0x27, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) out_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* The PiTFT (ili9340) has a hardware reset circuit that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * resets only on power-on and not on each reboot through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * a gpio like the rpi-display does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * As a result, we need to always apply the rotation value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * regardless of the display "on/off" state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	switch (dbidev->rotation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			    ILI9341_MADCTL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		addr_mode = ILI9341_MADCTL_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		addr_mode = ILI9341_MADCTL_MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		addr_mode = ILI9341_MADCTL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	addr_mode |= ILI9341_MADCTL_BGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct drm_simple_display_pipe_funcs mi0283qt_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.enable = mi0283qt_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.disable = mipi_dbi_pipe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.update = mipi_dbi_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct drm_display_mode mi0283qt_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	DRM_SIMPLE_MODE(320, 240, 58, 43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEFINE_DRM_GEM_CMA_FOPS(mi0283qt_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct drm_driver mi0283qt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.fops			= &mi0283qt_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.debugfs_init		= mipi_dbi_debugfs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.name			= "mi0283qt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.desc			= "Multi-Inno MI0283QT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.date			= "20160614",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.major			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.minor			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct of_device_id mi0283qt_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ .compatible = "multi-inno,mi0283qt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_DEVICE_TABLE(of, mi0283qt_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct spi_device_id mi0283qt_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ "mi0283qt", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_DEVICE_TABLE(spi, mi0283qt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int mi0283qt_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct mipi_dbi_dev *dbidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct mipi_dbi *dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct gpio_desc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u32 rotation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	dbidev = devm_drm_dev_alloc(dev, &mi0283qt_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				    struct mipi_dbi_dev, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (IS_ERR(dbidev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return PTR_ERR(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	drm = &dbidev->drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (IS_ERR(dbi->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return PTR_ERR(dbi->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (IS_ERR(dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return PTR_ERR(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dbidev->regulator = devm_regulator_get(dev, "power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (IS_ERR(dbidev->regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return PTR_ERR(dbidev->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	dbidev->backlight = devm_of_find_backlight(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (IS_ERR(dbidev->backlight))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return PTR_ERR(dbidev->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	device_property_read_u32(dev, "rotation", &rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ret = mipi_dbi_spi_init(spi, dbi, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = mipi_dbi_dev_init(dbidev, &mi0283qt_pipe_funcs, &mi0283qt_mode, rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	drm_mode_config_reset(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret = drm_dev_register(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	spi_set_drvdata(spi, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	drm_fbdev_generic_setup(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int mi0283qt_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct drm_device *drm = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	drm_dev_unplug(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	drm_atomic_helper_shutdown(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void mi0283qt_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int __maybe_unused mi0283qt_pm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return drm_mode_config_helper_suspend(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int __maybe_unused mi0283qt_pm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	drm_mode_config_helper_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct dev_pm_ops mi0283qt_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	SET_SYSTEM_SLEEP_PM_OPS(mi0283qt_pm_suspend, mi0283qt_pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct spi_driver mi0283qt_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.name = "mi0283qt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.of_match_table = mi0283qt_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.pm = &mi0283qt_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.id_table = mi0283qt_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.probe = mi0283qt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.remove = mi0283qt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.shutdown = mi0283qt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) module_spi_driver(mi0283qt_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_DESCRIPTION("Multi-Inno MI0283QT DRM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_AUTHOR("Noralf Trønnes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_LICENSE("GPL");