^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRM driver for Ilitek ILI9486 panels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2020 Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_mipi_dbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_modeset_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ILI9486_ITFCTR1 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ILI9486_PWCTRL1 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ILI9486_VMCTRL1 0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ILI9486_PGAMCTRL 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ILI9486_NGAMCTRL 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ILI9486_DGAMCTRL 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ILI9486_MADCTL_BGR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ILI9486_MADCTL_MV BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ILI9486_MADCTL_MX BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ILI9486_MADCTL_MY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * The PiScreen/waveshare rpi-lcd-35 has a SPI to 16-bit parallel bus converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * in front of the display controller. This means that 8-bit values have to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * transferred as 16-bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int waveshare_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) size_t num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct spi_device *spi = mipi->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void *data = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __be16 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) buf = kmalloc(32 * sizeof(u16), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * The displays are Raspberry Pi HATs and connected to the 8-bit only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * SPI controller, so 16-bit command and parameters need byte swapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * before being transferred as 8-bit on the big endian SPI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Pixel data bytes have already been swapped before this function is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) buf[0] = cpu_to_be16(*cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) gpiod_set_value_cansleep(mipi->dc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret || !num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* 8-bit configuration data, not 16-bit pixel data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (num <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) buf[i] = cpu_to_be16(par[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) num *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) gpiod_set_value_cansleep(mipi->dc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, data, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void waveshare_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mipi_dbi *dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!drm_dev_enter(pipe->crtc.dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DRM_DEBUG_KMS("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = mipi_dbi_poweron_conditional_reset(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mipi_dbi_command(dbi, ILI9486_ITFCTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msleep(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mipi_dbi_command(dbi, ILI9486_PWCTRL1, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mipi_dbi_command(dbi, ILI9486_VMCTRL1, 0x00, 0x00, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mipi_dbi_command(dbi, ILI9486_PGAMCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x0F, 0x1F, 0x1C, 0x0C, 0x0F, 0x08, 0x48, 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x37, 0x0A, 0x13, 0x04, 0x11, 0x0D, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mipi_dbi_command(dbi, ILI9486_NGAMCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mipi_dbi_command(dbi, ILI9486_DGAMCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) out_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (dbidev->rotation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) addr_mode = ILI9486_MADCTL_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) addr_mode = ILI9486_MADCTL_MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) addr_mode = ILI9486_MADCTL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) addr_mode = ILI9486_MADCTL_MV | ILI9486_MADCTL_MY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ILI9486_MADCTL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) addr_mode |= ILI9486_MADCTL_BGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct drm_simple_display_pipe_funcs waveshare_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .enable = waveshare_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .disable = mipi_dbi_pipe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .update = mipi_dbi_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct drm_display_mode waveshare_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DRM_SIMPLE_MODE(480, 320, 73, 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE_DRM_GEM_CMA_FOPS(ili9486_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct drm_driver ili9486_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .fops = &ili9486_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DRM_GEM_CMA_DRIVER_OPS_VMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .debugfs_init = mipi_dbi_debugfs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "ili9486",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .desc = "Ilitek ILI9486",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .date = "20200118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .major = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct of_device_id ili9486_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .compatible = "waveshare,rpi-lcd-35" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .compatible = "ozzmaker,piscreen" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_DEVICE_TABLE(of, ili9486_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct spi_device_id ili9486_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { "ili9486", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DEVICE_TABLE(spi, ili9486_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int ili9486_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mipi_dbi_dev *dbidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mipi_dbi *dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct gpio_desc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 rotation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dbidev = devm_drm_dev_alloc(dev, &ili9486_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct mipi_dbi_dev, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (IS_ERR(dbidev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return PTR_ERR(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) drm = &dbidev->drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (IS_ERR(dbi->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return PTR_ERR(dbi->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (IS_ERR(dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return PTR_ERR(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dbidev->backlight = devm_of_find_backlight(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (IS_ERR(dbidev->backlight))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return PTR_ERR(dbidev->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) device_property_read_u32(dev, "rotation", &rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = mipi_dbi_spi_init(spi, dbi, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dbi->command = waveshare_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dbi->read_commands = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = mipi_dbi_dev_init(dbidev, &waveshare_pipe_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) &waveshare_mode, rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) drm_mode_config_reset(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = drm_dev_register(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spi_set_drvdata(spi, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) drm_fbdev_generic_setup(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int ili9486_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct drm_device *drm = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) drm_dev_unplug(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) drm_atomic_helper_shutdown(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void ili9486_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) drm_atomic_helper_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct spi_driver ili9486_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "ili9486",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .of_match_table = ili9486_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .id_table = ili9486_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .probe = ili9486_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .remove = ili9486_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .shutdown = ili9486_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) module_spi_driver(ili9486_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_DESCRIPTION("Ilitek ILI9486 DRM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags