Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRM driver for Ilitek ILI9341 panels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on mi0283qt.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright 2016 Noralf Trønnes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <drm/drm_mipi_dbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <drm/drm_modeset_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ILI9341_FRMCTR1		0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ILI9341_DISCTRL		0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ILI9341_ETMOD		0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ILI9341_PWCTRL1		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ILI9341_PWCTRL2		0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ILI9341_VMCTRL1		0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ILI9341_VMCTRL2		0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ILI9341_PWCTRLA		0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ILI9341_PWCTRLB		0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ILI9341_PGAMCTRL	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ILI9341_NGAMCTRL	0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ILI9341_DTCTRLA		0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ILI9341_DTCTRLB		0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ILI9341_PWRSEQ		0xed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ILI9341_EN3GAM		0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ILI9341_PUMPCTRL	0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ILI9341_MADCTL_BGR	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ILI9341_MADCTL_MV	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ILI9341_MADCTL_MX	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ILI9341_MADCTL_MY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			     struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			     struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct mipi_dbi *dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u8 addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	DRM_DEBUG_KMS("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ret = mipi_dbi_poweron_conditional_reset(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		goto out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	mipi_dbi_command(dbi, ILI9341_PWCTRLB, 0x00, 0xc1, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mipi_dbi_command(dbi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	mipi_dbi_command(dbi, ILI9341_DTCTRLA, 0x85, 0x00, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	mipi_dbi_command(dbi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	mipi_dbi_command(dbi, ILI9341_PUMPCTRL, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	mipi_dbi_command(dbi, ILI9341_DTCTRLB, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* Power Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mipi_dbi_command(dbi, ILI9341_PWCTRL1, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mipi_dbi_command(dbi, ILI9341_PWCTRL2, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* VCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	mipi_dbi_command(dbi, ILI9341_VMCTRL1, 0x3e, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mipi_dbi_command(dbi, ILI9341_VMCTRL2, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Memory Access Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* Frame Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	mipi_dbi_command(dbi, ILI9341_FRMCTR1, 0x00, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* Gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	mipi_dbi_command(dbi, ILI9341_EN3GAM, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mipi_dbi_command(dbi, ILI9341_PGAMCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	mipi_dbi_command(dbi, ILI9341_NGAMCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* DDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mipi_dbi_command(dbi, ILI9341_ETMOD, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mipi_dbi_command(dbi, ILI9341_DISCTRL, 0x08, 0x82, 0x27, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) out_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	switch (dbidev->rotation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		addr_mode = ILI9341_MADCTL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		addr_mode = ILI9341_MADCTL_MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		addr_mode = ILI9341_MADCTL_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			    ILI9341_MADCTL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	addr_mode |= ILI9341_MADCTL_BGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct drm_simple_display_pipe_funcs ili9341_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.enable = yx240qv29_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.disable = mipi_dbi_pipe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.update = mipi_dbi_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct drm_display_mode yx240qv29_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	DRM_SIMPLE_MODE(240, 320, 37, 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEFINE_DRM_GEM_CMA_FOPS(ili9341_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct drm_driver ili9341_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.fops			= &ili9341_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.debugfs_init		= mipi_dbi_debugfs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.name			= "ili9341",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.desc			= "Ilitek ILI9341",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.date			= "20180514",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.major			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.minor			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct of_device_id ili9341_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ .compatible = "adafruit,yx240qv29" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MODULE_DEVICE_TABLE(of, ili9341_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct spi_device_id ili9341_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ "yx240qv29", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_DEVICE_TABLE(spi, ili9341_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ili9341_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct mipi_dbi_dev *dbidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct mipi_dbi *dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct gpio_desc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 rotation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	dbidev = devm_drm_dev_alloc(dev, &ili9341_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				    struct mipi_dbi_dev, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (IS_ERR(dbidev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return PTR_ERR(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	drm = &dbidev->drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (IS_ERR(dbi->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return PTR_ERR(dbi->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (IS_ERR(dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return PTR_ERR(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	dbidev->backlight = devm_of_find_backlight(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (IS_ERR(dbidev->backlight))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return PTR_ERR(dbidev->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	device_property_read_u32(dev, "rotation", &rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ret = mipi_dbi_spi_init(spi, dbi, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = mipi_dbi_dev_init(dbidev, &ili9341_pipe_funcs, &yx240qv29_mode, rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	drm_mode_config_reset(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ret = drm_dev_register(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	spi_set_drvdata(spi, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	drm_fbdev_generic_setup(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ili9341_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct drm_device *drm = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	drm_dev_unplug(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	drm_atomic_helper_shutdown(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void ili9341_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct spi_driver ili9341_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.name = "ili9341",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.of_match_table = ili9341_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.id_table = ili9341_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.probe = ili9341_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.remove = ili9341_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.shutdown = ili9341_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) module_spi_driver(ili9341_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DESCRIPTION("Ilitek ILI9341 DRM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_AUTHOR("David Lechner <david@lechnology.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MODULE_LICENSE("GPL");