Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRM driver for the HX8357D LCD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2018 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright 2016 Noralf Trønnes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2015 Adafruit Industries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2013 Christian Vogelgsang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <drm/drm_mipi_dbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <drm/drm_modeset_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HX8357D_SETOSC 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HX8357D_SETPOWER 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HX8357D_SETRGB 0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define HX8357D_SETCYC 0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HX8357D_SETCOM 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HX8357D_SETEXTC 0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HX8357D_SETSTBA 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define HX8357D_SETPANEL 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HX8357D_SETGAMMA 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HX8357D_MADCTL_MY  0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HX8357D_MADCTL_MX  0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HX8357D_MADCTL_MV  0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HX8357D_MADCTL_ML  0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HX8357D_MADCTL_RGB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HX8357D_MADCTL_BGR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HX8357D_MADCTL_MH  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			     struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			     struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct mipi_dbi *dbi = &dbidev->dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u8 addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DRM_DEBUG_KMS("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	ret = mipi_dbi_poweron_conditional_reset(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		goto out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		goto out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* setextc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	mipi_dbi_command(dbi, HX8357D_SETEXTC, 0xFF, 0x83, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* setRGB which also enables SDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	mipi_dbi_command(dbi, HX8357D_SETRGB, 0x00, 0x00, 0x06, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* -1.52V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	mipi_dbi_command(dbi, HX8357D_SETCOM, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* Normal mode 70Hz, Idle mode 55 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	mipi_dbi_command(dbi, HX8357D_SETOSC, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* Set Panel - BGR, Gate direction swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mipi_dbi_command(dbi, HX8357D_SETPANEL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mipi_dbi_command(dbi, HX8357D_SETPOWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			 0x00,  /* Not deep standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			 0x15,  /* BT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			 0x1C,  /* VSPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			 0x1C,  /* VSNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			 0x83,  /* AP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			 0xAA);  /* FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	mipi_dbi_command(dbi, HX8357D_SETSTBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			 0x50,  /* OPON normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			 0x50,  /* OPON idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			 0x01,  /* STBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			 0x3C,  /* STBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			 0x1E,  /* STBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			 0x08);  /* GEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	mipi_dbi_command(dbi, HX8357D_SETCYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			 0x02,  /* NW 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			 0x40,  /* RTN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			 0x00,  /* DIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			 0x2A,  /* DUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			 0x2A,  /* DUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			 0x0D,  /* GDON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			 0x78);  /* GDOFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mipi_dbi_command(dbi, HX8357D_SETGAMMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			 0x4b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			 0x4b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			 0x4b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			 0x4b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			 MIPI_DCS_PIXEL_FMT_16BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* TE off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_ON, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* tear line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_SCANLINE, 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* Exit Sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* display on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) out_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	switch (dbidev->rotation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		addr_mode = HX8357D_MADCTL_MX | HX8357D_MADCTL_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		addr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct drm_simple_display_pipe_funcs hx8357d_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.enable = yx240qv29_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.disable = mipi_dbi_pipe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.update = mipi_dbi_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct drm_display_mode yx350hv15_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	DRM_SIMPLE_MODE(320, 480, 60, 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DEFINE_DRM_GEM_CMA_FOPS(hx8357d_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct drm_driver hx8357d_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.fops			= &hx8357d_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.debugfs_init		= mipi_dbi_debugfs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.name			= "hx8357d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.desc			= "HX8357D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.date			= "20181023",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.major			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.minor			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct of_device_id hx8357d_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{ .compatible = "adafruit,yx350hv15" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_DEVICE_TABLE(of, hx8357d_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct spi_device_id hx8357d_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	{ "yx350hv15", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MODULE_DEVICE_TABLE(spi, hx8357d_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int hx8357d_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct mipi_dbi_dev *dbidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct drm_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct gpio_desc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u32 rotation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	dbidev = devm_drm_dev_alloc(dev, &hx8357d_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				    struct mipi_dbi_dev, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (IS_ERR(dbidev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return PTR_ERR(dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	drm = &dbidev->drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (IS_ERR(dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return PTR_ERR(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	dbidev->backlight = devm_of_find_backlight(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (IS_ERR(dbidev->backlight))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return PTR_ERR(dbidev->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	device_property_read_u32(dev, "rotation", &rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ret = mipi_dbi_spi_init(spi, &dbidev->dbi, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ret = mipi_dbi_dev_init(dbidev, &hx8357d_pipe_funcs, &yx350hv15_mode, rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	drm_mode_config_reset(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = drm_dev_register(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	spi_set_drvdata(spi, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	drm_fbdev_generic_setup(drm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int hx8357d_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct drm_device *drm = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	drm_dev_unplug(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	drm_atomic_helper_shutdown(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void hx8357d_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct spi_driver hx8357d_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.name = "hx8357d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.of_match_table = hx8357d_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.id_table = hx8357d_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.probe = hx8357d_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.remove = hx8357d_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.shutdown = hx8357d_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) module_spi_driver(hx8357d_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_DESCRIPTION("HX8357D DRM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_LICENSE("GPL");