^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012-2019 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Public License version 2. See the file COPYING in the main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * directory of this archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Authors: Matthew Garrett
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Gerd Hoffmann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Portions of this code derived from cirrusfb.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <video/cirrus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_atomic_state_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <drm/drm_damage_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <drm/drm_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_format_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <drm/drm_gem_shmem_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <drm/drm_ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <drm/drm_managed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <drm/drm_modeset_helper_vtables.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRIVER_NAME "cirrus"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRIVER_DESC "qemu cirrus vga"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRIVER_DATE "2019"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRIVER_MAJOR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRIVER_MINOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CIRRUS_MAX_PITCH (0x1FF << 3) /* (4096 - 1) & ~111b bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CIRRUS_VRAM_SIZE (4 * 1024 * 1024) /* 4 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct cirrus_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct drm_device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct drm_simple_display_pipe pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct drm_connector conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *vram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define to_cirrus(_dev) container_of(_dev, struct cirrus_device, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * The meat of this driver. The core passes us a mode and we have to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * it. The modesetting here is the bare minimum required to satisfy the qemu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * emulation of this hardware, and running this against a real device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * likely to result in an inadequately programmed mode. We've already had
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * the opportunity to modify the mode, so whatever we receive here should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * be something that can be correctly programmed and displayed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SEQ_INDEX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SEQ_DATA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static u8 rreg_seq(struct cirrus_device *cirrus, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) iowrite8(reg, cirrus->mmio + SEQ_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ioread8(cirrus->mmio + SEQ_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void wreg_seq(struct cirrus_device *cirrus, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) iowrite8(reg, cirrus->mmio + SEQ_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) iowrite8(val, cirrus->mmio + SEQ_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CRT_INDEX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CRT_DATA 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static u8 rreg_crt(struct cirrus_device *cirrus, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite8(reg, cirrus->mmio + CRT_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ioread8(cirrus->mmio + CRT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) iowrite8(reg, cirrus->mmio + CRT_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) iowrite8(val, cirrus->mmio + CRT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GFX_INDEX 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GFX_DATA 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void wreg_gfx(struct cirrus_device *cirrus, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) iowrite8(reg, cirrus->mmio + GFX_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iowrite8(val, cirrus->mmio + GFX_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VGA_DAC_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void wreg_hdr(struct cirrus_device *cirrus, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ioread8(cirrus->mmio + VGA_DAC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ioread8(cirrus->mmio + VGA_DAC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ioread8(cirrus->mmio + VGA_DAC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ioread8(cirrus->mmio + VGA_DAC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iowrite8(val, cirrus->mmio + VGA_DAC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int cirrus_convert_to(struct drm_framebuffer *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (fb->format->cpp[0] == 4 && fb->pitches[0] > CIRRUS_MAX_PITCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (fb->width * 3 <= CIRRUS_MAX_PITCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* convert from XR24 to RG24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* convert from XR24 to RG16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int cirrus_cpp(struct drm_framebuffer *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int convert_cpp = cirrus_convert_to(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (convert_cpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return convert_cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return fb->format->cpp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int cirrus_pitch(struct drm_framebuffer *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int convert_cpp = cirrus_convert_to(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (convert_cpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return convert_cpp * fb->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return fb->pitches[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void cirrus_set_start_address(struct cirrus_device *cirrus, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!drm_dev_enter(&cirrus->dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) addr = offset >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) wreg_crt(cirrus, 0x0c, (u8)((addr >> 8) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) wreg_crt(cirrus, 0x0d, (u8)(addr & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tmp = rreg_crt(cirrus, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tmp &= 0xf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tmp |= (addr >> 16) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) tmp |= (addr >> 15) & 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) wreg_crt(cirrus, 0x1b, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tmp = rreg_crt(cirrus, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tmp &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tmp |= (addr >> 12) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) wreg_crt(cirrus, 0x1d, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int cirrus_mode_set(struct cirrus_device *cirrus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct drm_framebuffer *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int hsyncstart, hsyncend, htotal, hdispend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int vtotal, vdispend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int tmp, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int sr07 = 0, hdr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!drm_dev_enter(&cirrus->dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) htotal = mode->htotal / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) hsyncend = mode->hsync_end / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) hsyncstart = mode->hsync_start / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) hdispend = mode->hdisplay / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) vtotal = mode->vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) vdispend = mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) vdispend -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) vtotal -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) htotal -= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) hdispend -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) hsyncstart += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hsyncend += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) wreg_crt(cirrus, VGA_CRTC_V_SYNC_END, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) wreg_crt(cirrus, VGA_CRTC_H_TOTAL, htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) wreg_crt(cirrus, VGA_CRTC_H_DISP, hdispend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) wreg_crt(cirrus, VGA_CRTC_H_SYNC_START, hsyncstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) wreg_crt(cirrus, VGA_CRTC_H_SYNC_END, hsyncend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) wreg_crt(cirrus, VGA_CRTC_V_TOTAL, vtotal & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) wreg_crt(cirrus, VGA_CRTC_V_DISP_END, vdispend & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmp = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if ((vdispend + 1) & 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) wreg_crt(cirrus, VGA_CRTC_MAX_SCAN, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Overflow bits for values that don't fit in the standard registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tmp = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (vtotal & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tmp |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (vdispend & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tmp |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if ((vdispend + 1) & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tmp |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (vtotal & 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (vdispend & 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tmp |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) wreg_crt(cirrus, VGA_CRTC_OVERFLOW, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* More overflow bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if ((htotal + 5) & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tmp |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if ((htotal + 5) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (vtotal & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tmp |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (vtotal & 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tmp |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) wreg_crt(cirrus, CL_CRT1A, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Disable Hercules/CGA compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) wreg_crt(cirrus, VGA_CRTC_MODE, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sr07 = rreg_seq(cirrus, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sr07 &= 0xe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) hdr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cirrus->cpp = cirrus_cpp(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) switch (cirrus->cpp * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sr07 |= 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sr07 |= 0x17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) hdr = 0xc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) sr07 |= 0x15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) hdr = 0xc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sr07 |= 0x19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) hdr = 0xc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wreg_seq(cirrus, 0x7, sr07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Program the pitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cirrus->pitch = cirrus_pitch(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tmp = cirrus->pitch / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) wreg_crt(cirrus, VGA_CRTC_OFFSET, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Enable extended blanking and pitch bits, and enable full memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tmp = 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tmp |= (cirrus->pitch >> 7) & 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tmp |= (cirrus->pitch >> 6) & 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) wreg_crt(cirrus, 0x1b, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Enable high-colour modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) wreg_gfx(cirrus, VGA_GFX_MODE, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* And set graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) wreg_gfx(cirrus, VGA_GFX_MISC, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) wreg_hdr(cirrus, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cirrus_set_start_address(cirrus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Unblank (needed on S3 resume, vgabios doesn't do it then) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) outb(0x20, 0x3c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int cirrus_fb_blit_rect(struct drm_framebuffer *fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct drm_rect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct cirrus_device *cirrus = to_cirrus(fb->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void *vmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!drm_dev_enter(&cirrus->dev, &idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) vmap = drm_gem_shmem_vmap(fb->obj[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!vmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) goto out_dev_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (cirrus->cpp == fb->format->cpp[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) drm_fb_memcpy_dstclip(cirrus->vram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) vmap, fb, rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) else if (fb->format->cpp[0] == 4 && cirrus->cpp == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) drm_fb_xrgb8888_to_rgb565_dstclip(cirrus->vram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cirrus->pitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) vmap, fb, rect, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else if (fb->format->cpp[0] == 4 && cirrus->cpp == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) drm_fb_xrgb8888_to_rgb888_dstclip(cirrus->vram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cirrus->pitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vmap, fb, rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) WARN_ON_ONCE("cpp mismatch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) drm_gem_shmem_vunmap(fb->obj[0], vmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) out_dev_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) drm_dev_exit(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int cirrus_fb_blit_fullscreen(struct drm_framebuffer *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct drm_rect fullscreen = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .x1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .x2 = fb->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .y1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .y2 = fb->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return cirrus_fb_blit_rect(fb, &fullscreen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int cirrus_check_size(int width, int height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct drm_framebuffer *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int pitch = width * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pitch = cirrus_pitch(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (pitch > CIRRUS_MAX_PITCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (pitch * height > CIRRUS_VRAM_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* cirrus connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int cirrus_conn_get_modes(struct drm_connector *conn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) count = drm_add_modes_noedid(conn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) conn->dev->mode_config.max_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) conn->dev->mode_config.max_height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) drm_set_preferred_mode(conn, 1024, 768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct drm_connector_helper_funcs cirrus_conn_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .get_modes = cirrus_conn_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct drm_connector_funcs cirrus_conn_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .destroy = drm_connector_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int cirrus_conn_init(struct cirrus_device *cirrus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) drm_connector_helper_add(&cirrus->conn, &cirrus_conn_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return drm_connector_init(&cirrus->dev, &cirrus->conn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &cirrus_conn_funcs, DRM_MODE_CONNECTOR_VGA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* cirrus (simple) display pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static enum drm_mode_status cirrus_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (cirrus_check_size(mode->hdisplay, mode->vdisplay, NULL) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return MODE_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int cirrus_pipe_check(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct drm_plane_state *plane_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct drm_crtc_state *crtc_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct drm_framebuffer *fb = plane_state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return cirrus_check_size(fb->width, fb->height, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void cirrus_pipe_enable(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct drm_plane_state *plane_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct cirrus_device *cirrus = to_cirrus(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cirrus_mode_set(cirrus, &crtc_state->mode, plane_state->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cirrus_fb_blit_fullscreen(plane_state->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void cirrus_pipe_update(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct cirrus_device *cirrus = to_cirrus(pipe->crtc.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct drm_plane_state *state = pipe->plane.state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct drm_crtc *crtc = &pipe->crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct drm_rect rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (pipe->plane.state->fb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cirrus->cpp != cirrus_cpp(pipe->plane.state->fb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cirrus_mode_set(cirrus, &crtc->mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pipe->plane.state->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (drm_atomic_helper_damage_merged(old_state, state, &rect))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cirrus_fb_blit_rect(pipe->plane.state->fb, &rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct drm_simple_display_pipe_funcs cirrus_pipe_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .mode_valid = cirrus_pipe_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .check = cirrus_pipe_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .enable = cirrus_pipe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .update = cirrus_pipe_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const uint32_t cirrus_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DRM_FORMAT_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) DRM_FORMAT_RGB888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DRM_FORMAT_XRGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const uint64_t cirrus_modifiers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DRM_FORMAT_MOD_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DRM_FORMAT_MOD_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int cirrus_pipe_init(struct cirrus_device *cirrus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return drm_simple_display_pipe_init(&cirrus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &cirrus->pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &cirrus_pipe_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cirrus_formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ARRAY_SIZE(cirrus_formats),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cirrus_modifiers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &cirrus->conn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* cirrus framebuffers & mode config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static struct drm_framebuffer*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cirrus_fb_create(struct drm_device *dev, struct drm_file *file_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) const struct drm_mode_fb_cmd2 *mode_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (mode_cmd->pixel_format != DRM_FORMAT_RGB565 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mode_cmd->pixel_format != DRM_FORMAT_RGB888 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mode_cmd->pixel_format != DRM_FORMAT_XRGB8888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (cirrus_check_size(mode_cmd->width, mode_cmd->height, NULL) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return drm_gem_fb_create_with_dirty(dev, file_priv, mode_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct drm_mode_config_funcs cirrus_mode_config_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .fb_create = cirrus_fb_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .atomic_check = drm_atomic_helper_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .atomic_commit = drm_atomic_helper_commit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int cirrus_mode_config_init(struct cirrus_device *cirrus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct drm_device *dev = &cirrus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = drmm_mode_config_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev->mode_config.min_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev->mode_config.min_height = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev->mode_config.max_width = CIRRUS_MAX_PITCH / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev->mode_config.max_height = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev->mode_config.preferred_depth = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev->mode_config.prefer_shadow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev->mode_config.funcs = &cirrus_mode_config_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DEFINE_DRM_GEM_FOPS(cirrus_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct drm_driver cirrus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .desc = DRIVER_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .date = DRIVER_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .major = DRIVER_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .minor = DRIVER_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .fops = &cirrus_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DRM_GEM_SHMEM_DRIVER_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int cirrus_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct drm_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct cirrus_device *cirrus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "cirrusdrmfb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = pci_request_regions(pdev, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) cirrus = devm_drm_dev_alloc(&pdev->dev, &cirrus_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct cirrus_device, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (IS_ERR(cirrus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return PTR_ERR(cirrus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev = &cirrus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) cirrus->vram = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (cirrus->vram == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) cirrus->mmio = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pci_resource_len(pdev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (cirrus->mmio == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = cirrus_mode_config_init(cirrus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = cirrus_conn_init(cirrus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = cirrus_pipe_init(cirrus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) drm_mode_config_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = drm_dev_register(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static void cirrus_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct drm_device *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) drm_dev_unplug(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) drm_atomic_helper_shutdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const struct pci_device_id pciidlist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .vendor = PCI_VENDOR_ID_CIRRUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .device = PCI_DEVICE_ID_CIRRUS_5446,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* only bind to the cirrus chip in qemu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .subvendor = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .subdevice = PCI_SUBDEVICE_ID_QEMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .vendor = PCI_VENDOR_ID_CIRRUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .device = PCI_DEVICE_ID_CIRRUS_5446,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .subvendor = PCI_VENDOR_ID_XEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .subdevice = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { /* end if list */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static struct pci_driver cirrus_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .id_table = pciidlist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .probe = cirrus_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .remove = cirrus_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int __init cirrus_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (vgacon_text_force())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return pci_register_driver(&cirrus_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void __exit cirrus_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pci_unregister_driver(&cirrus_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) module_init(cirrus_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) module_exit(cirrus_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MODULE_DEVICE_TABLE(pci, pciidlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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