Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2015, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef TEGRA_VIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define TEGRA_VIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* VIC methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VIC_SET_APPLICATION_ID			0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VIC_SET_FCE_UCODE_SIZE			0x0000071C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define VIC_SET_FCE_UCODE_OFFSET		0x0000072C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* VIC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VIC_THI_STREAMID0	0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VIC_THI_STREAMID1	0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NV_PVIC_MISC_PRI_VIC_CG			0x000016d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CG_IDLE_CG_DLY_CNT(val)			((val & 0x3f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CG_IDLE_CG_EN				(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CG_WAKEUP_DLY_CNT(val)			((val & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIC_TFBIF_TRANSCFG	0x00002044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define  TRANSCFG_ATT(i, v)	(((v) & 0x3) << (i * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define  TRANSCFG_SID_HW	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define  TRANSCFG_SID_PHY	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define  TRANSCFG_SID_FALCON	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Firmware offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VIC_UCODE_FCE_HEADER_OFFSET		(6*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VIC_UCODE_FCE_DATA_OFFSET		(7*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FCE_UCODE_SIZE_OFFSET			(2*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif /* TEGRA_VIC_H */