^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/host1x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "falcon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "vic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct vic_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const char *firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bool supports_sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct vic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct falcon falcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) bool booted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct tegra_drm_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct host1x_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Platform configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const struct vic_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline struct vic *to_vic(struct tegra_drm_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return container_of(client, struct vic, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) writel(value, vic->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int vic_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct vic *vic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) err = clk_prepare_enable(vic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err = reset_control_deassert(vic->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clk_disable_unprepare(vic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int vic_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct vic *vic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) err = reset_control_assert(vic->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_disable_unprepare(vic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) vic->booted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int vic_boot(struct vic *vic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifdef CONFIG_IOMMU_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 fce_ucode_size, fce_bin_data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (vic->booted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_IOMMU_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (vic->config->supports_sid && spec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) TRANSCFG_ATT(0, TRANSCFG_SID_HW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) vic_writel(vic, value, VIC_TFBIF_TRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (spec->num_ids > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) value = spec->ids[0] & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) vic_writel(vic, value, VIC_THI_STREAMID0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) vic_writel(vic, value, VIC_THI_STREAMID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* setup clockgating registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CG_IDLE_CG_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CG_WAKEUP_DLY_CNT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) NV_PVIC_MISC_PRI_VIC_CG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) err = falcon_boot(&vic->falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) hdr = vic->falcon.firmware.virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) hdr = vic->falcon.firmware.virt +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fce_ucode_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (vic->falcon.firmware.iova + fce_bin_data_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) err = falcon_wait_idle(&vic->falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(vic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "failed to set application ID and FCE base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) vic->booted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int vic_init(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct tegra_drm_client *drm = host1x_to_drm_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct drm_device *dev = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct tegra_drm *tegra = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct vic *vic = to_vic(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err = host1x_client_iommu_attach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (err < 0 && err != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_err(vic->dev, "failed to attach to domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) vic->channel = host1x_channel_request(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!vic->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) client->syncpts[0] = host1x_syncpt_request(client, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!client->syncpts[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto free_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) err = tegra_drm_register_client(tegra, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto free_syncpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Inherit the DMA parameters (such as maximum segment size) from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * parent host1x device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) client->dev->dma_parms = client->host->dma_parms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) free_syncpt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) host1x_syncpt_free(client->syncpts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) free_channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) host1x_channel_put(vic->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) detach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) host1x_client_iommu_detach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int vic_exit(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct tegra_drm_client *drm = host1x_to_drm_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct drm_device *dev = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct tegra_drm *tegra = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct vic *vic = to_vic(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* avoid a dangling pointer just in case this disappears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) client->dev->dma_parms = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) err = tegra_drm_unregister_client(tegra, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) host1x_syncpt_free(client->syncpts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) host1x_channel_put(vic->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) host1x_client_iommu_detach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (client->group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dma_unmap_single(vic->dev, vic->falcon.firmware.phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) vic->falcon.firmware.size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tegra_drm_free(tegra, vic->falcon.firmware.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) vic->falcon.firmware.virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) vic->falcon.firmware.iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dma_free_coherent(vic->dev, vic->falcon.firmware.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) vic->falcon.firmware.virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) vic->falcon.firmware.iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct host1x_client_ops vic_client_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .init = vic_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .exit = vic_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int vic_load_firmware(struct vic *vic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct host1x_client *client = &vic->client.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct tegra_drm *tegra = vic->client.drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dma_addr_t iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (vic->falcon.firmware.virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) size = vic->falcon.firmware.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!client->group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) virt = tegra_drm_alloc(tegra, size, &iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) vic->falcon.firmware.virt = virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) vic->falcon.firmware.iova = iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) err = falcon_load_firmware(&vic->falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * In this case we have received an IOVA from the shared domain, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * need to make sure to get the physical address so that the DMA API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * knows what memory pages to flush the cache for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (client->group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err = dma_mapping_error(vic->dev, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) vic->falcon.firmware.phys = phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!client->group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dma_free_coherent(vic->dev, size, virt, iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tegra_drm_free(tegra, size, virt, iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int vic_open_channel(struct tegra_drm_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct tegra_drm_context *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct vic *vic = to_vic(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) err = pm_runtime_resume_and_get(vic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) err = vic_load_firmware(vic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) goto rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) err = vic_boot(vic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) context->channel = host1x_channel_get(vic->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!context->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rpm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pm_runtime_put(vic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void vic_close_channel(struct tegra_drm_context *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct vic *vic = to_vic(context->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) host1x_channel_put(context->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pm_runtime_put(vic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct tegra_drm_client_ops vic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .open_channel = vic_open_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .close_channel = vic_close_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .submit = tegra_drm_submit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct vic_config vic_t124_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .version = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .supports_sid = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct vic_config vic_t210_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .version = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .supports_sid = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct vic_config vic_t186_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .version = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .supports_sid = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct vic_config vic_t194_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .version = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .supports_sid = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct of_device_id tegra_vic_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MODULE_DEVICE_TABLE(of, tegra_vic_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int vic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct host1x_syncpt **syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct vic *vic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* inherit DMA mask from host1x parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!vic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) vic->config = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!syncpts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_err(&pdev->dev, "failed to get registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) vic->regs = devm_ioremap_resource(dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (IS_ERR(vic->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return PTR_ERR(vic->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) vic->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (IS_ERR(vic->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return PTR_ERR(vic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!dev->pm_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) vic->rst = devm_reset_control_get(dev, "vic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (IS_ERR(vic->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(&pdev->dev, "failed to get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return PTR_ERR(vic->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) vic->falcon.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) vic->falcon.regs = vic->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) err = falcon_init(&vic->falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) platform_set_drvdata(pdev, vic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) INIT_LIST_HEAD(&vic->client.base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) vic->client.base.ops = &vic_client_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) vic->client.base.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) vic->client.base.class = HOST1X_CLASS_VIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) vic->client.base.syncpts = syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) vic->client.base.num_syncpts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) vic->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) INIT_LIST_HEAD(&vic->client.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) vic->client.version = vic->config->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) vic->client.ops = &vic_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) err = host1x_client_register(&vic->client.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(dev, "failed to register host1x client: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto exit_falcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) err = vic_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto unregister_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unregister_client:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) host1x_client_unregister(&vic->client.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) exit_falcon:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) falcon_exit(&vic->falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int vic_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct vic *vic = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err = host1x_client_unregister(&vic->client.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (pm_runtime_enabled(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) vic_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) falcon_exit(&vic->falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct dev_pm_ops vic_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct platform_driver tegra_vic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = "tegra-vic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .of_match_table = tegra_vic_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .pm = &vic_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .probe = vic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .remove = vic_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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