^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 Avionic Design GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <drm/drm_bridge_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "dc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct tegra_rgb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct tegra_output output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct tegra_dc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return container_of(output, struct tegra_rgb, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct reg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct reg_entry rgb_enable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct reg_entry rgb_disable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void tegra_dc_write_regs(struct tegra_dc *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct reg_entry *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tegra_dc_writel(dc, table[i].value, table[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct tegra_rgb *rgb = to_rgb(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tegra_dc_commit(rgb->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct tegra_rgb *rgb = to_rgb(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* XXX: parameterize? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) value &= ~LVS_OUTPUT_POLARITY_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) value &= ~LHS_OUTPUT_POLARITY_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* XXX: parameterize? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DISP_ORDER_RED_BLUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* XXX: parameterize? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tegra_dc_commit(rgb->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long pclk = crtc_state->mode.clock * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct tegra_rgb *rgb = to_rgb(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * We may not want to change the frequency of the parent clock, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * it may be a parent for other peripherals. This is due to the fact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * that on Tegra20 there's only a single clock dedicated to display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * (pll_d_out0), whereas later generations have a second one that can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * be used to independently drive a second output (pll_d2_out0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * As a way to support multiple outputs on Tegra20 as well, pll_p is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * typically used as the parent clock for the display controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * But this comes at a cost: pll_p is the parent of several other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * peripherals, so its frequency shouldn't change out of the blue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * The best we can do at this point is to use the shift clock divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * and hope that the desired frequency can be matched (or at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * matched sufficiently close that the panel will still work).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pclk, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .disable = tegra_rgb_encoder_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .enable = tegra_rgb_encoder_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .atomic_check = tegra_rgb_encoder_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int tegra_dc_rgb_probe(struct tegra_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct tegra_rgb *rgb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) np = of_get_child_by_name(dc->dev->of_node, "rgb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!np || !of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!rgb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rgb->output.dev = dc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rgb->output.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rgb->dc = dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) err = tegra_output_probe(&rgb->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rgb->clk = devm_clk_get(dc->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (IS_ERR(rgb->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_err(dc->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return PTR_ERR(rgb->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rgb->clk_parent = devm_clk_get(dc->dev, "parent");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (IS_ERR(rgb->clk_parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(dc->dev, "failed to get parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return PTR_ERR(rgb->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) err = clk_set_parent(rgb->clk, rgb->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_err(dc->dev, "failed to set parent clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dc->rgb = &rgb->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int tegra_dc_rgb_remove(struct tegra_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!dc->rgb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tegra_output_remove(dc->rgb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dc->rgb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct tegra_output *output = dc->rgb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct drm_connector *connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!dc->rgb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) drm_encoder_helper_add(&output->encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &tegra_rgb_encoder_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Wrap directly-connected panel into DRM bridge in order to let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * DRM core to handle panel for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (output->panel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) output->bridge = devm_drm_panel_bridge_add(output->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) output->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (IS_ERR(output->bridge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(output->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "failed to wrap panel into bridge: %pe\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) output->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return PTR_ERR(output->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) output->panel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Tegra devices that have LVDS panel utilize LVDS encoder bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * go to display panel's receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Encoder usually have a power-down control which needs to be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * in order to transmit data to the panel. Historically devices that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * use an older device-tree version didn't model the bridge, assuming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * that encoder is turned ON by default, while today's DRM allows us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * to model LVDS encoder properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Newer device-trees utilize LVDS encoder bridge, which provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * us with a connector and handles the display panel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * For older device-trees we wrapped panel into the panel-bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (output->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) err = drm_bridge_attach(&output->encoder, output->bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(output->dev, "failed to attach bridge: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) connector = drm_bridge_connector_init(drm, &output->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (IS_ERR(connector)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(output->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "failed to initialize bridge connector: %pe\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return PTR_ERR(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) drm_connector_attach_encoder(connector, &output->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) err = tegra_output_init(drm, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(output->dev, "failed to initialize output: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Other outputs can be attached to either display controller. The RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * outputs are an exception and work only with their parent display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int tegra_dc_rgb_exit(struct tegra_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (dc->rgb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tegra_output_exit(dc->rgb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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