Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef TEGRA_PLANE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define TEGRA_PLANE_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <drm/drm_plane.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct tegra_bo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct tegra_dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct tegra_plane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	struct drm_plane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct tegra_dc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct tegra_cursor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct tegra_plane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct tegra_bo *bo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	unsigned int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	return container_of(plane, struct tegra_plane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct tegra_plane_legacy_blending_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	bool alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	bool top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct tegra_plane_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct drm_plane_state base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	struct sg_table *sgt[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	dma_addr_t iova[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	struct tegra_bo_tiling tiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u32 swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	bool reflect_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	bool reflect_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* used for legacy blending support only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	struct tegra_plane_legacy_blending_state blending[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	bool opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline struct tegra_plane_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) to_tegra_plane_state(struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		return container_of(state, struct tegra_plane_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern const struct drm_plane_funcs tegra_plane_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int tegra_plane_prepare_fb(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			   struct drm_plane_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void tegra_plane_cleanup_fb(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			    struct drm_plane_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int tegra_plane_state_add(struct tegra_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 			  struct drm_plane_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool tegra_plane_format_is_yuv(unsigned int format, bool *planar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 				   struct tegra_plane_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif /* TEGRA_PLANE_H */