Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <drm/drm_atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <drm/drm_plane_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "dc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "plane.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static void tegra_plane_destroy(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct tegra_plane *p = to_tegra_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	drm_plane_cleanup(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static void tegra_plane_reset(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct tegra_plane *p = to_tegra_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct tegra_plane_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	if (plane->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		__drm_atomic_helper_plane_destroy_state(plane->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	kfree(plane->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	plane->state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		plane->state = &state->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		plane->state->plane = plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		plane->state->zpos = p->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		plane->state->normalized_zpos = p->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			state->iova[i] = DMA_MAPPING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct drm_plane_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct tegra_plane_state *copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	copy = kmalloc(sizeof(*copy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (!copy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	__drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	copy->tiling = state->tiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	copy->format = state->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	copy->swap = state->swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	copy->reflect_x = state->reflect_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	copy->reflect_y = state->reflect_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	copy->opaque = state->opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		copy->blending[i] = state->blending[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		copy->iova[i] = DMA_MAPPING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		copy->sgt[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return &copy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 					     struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	__drm_atomic_helper_plane_destroy_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static bool tegra_plane_format_mod_supported(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					     uint32_t format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 					     uint64_t modifier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	const struct drm_format_info *info = drm_format_info(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (modifier == DRM_FORMAT_MOD_LINEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (info->num_planes == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct drm_plane_funcs tegra_plane_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.update_plane = drm_atomic_helper_update_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.disable_plane = drm_atomic_helper_disable_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.destroy = tegra_plane_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.reset = tegra_plane_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.atomic_destroy_state = tegra_plane_atomic_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.format_mod_supported = tegra_plane_format_mod_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct iommu_domain *domain = iommu_get_domain_for_dev(dc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	for (i = 0; i < state->base.fb->format->num_planes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		dma_addr_t phys_addr, *phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		struct sg_table *sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (!domain || dc->client.group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			phys = &phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		sgt = host1x_bo_pin(dc->dev, &bo->base, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (IS_ERR(sgt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			err = PTR_ERR(sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			goto unpin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (sgt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			err = dma_map_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				goto unpin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			 * The display controller needs contiguous memory, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			 * fail if the buffer is discontiguous and we fail to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			 * map its SG table to a single contiguous chunk of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			 * I/O virtual memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			if (sgt->nents > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				goto unpin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			state->iova[i] = sg_dma_address(sgt->sgl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			state->sgt[i] = sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			state->iova[i] = phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unpin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	dev_err(dc->dev, "failed to map plane %u: %d\n", i, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		struct sg_table *sgt = state->sgt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (sgt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		host1x_bo_unpin(dc->dev, &bo->base, sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		state->iova[i] = DMA_MAPPING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		state->sgt[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	for (i = 0; i < state->base.fb->format->num_planes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		struct sg_table *sgt = state->sgt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (sgt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		host1x_bo_unpin(dc->dev, &bo->base, sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		state->iova[i] = DMA_MAPPING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		state->sgt[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int tegra_plane_prepare_fb(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			   struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct tegra_dc *dc = to_tegra_dc(state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (!state->fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	drm_gem_fb_prepare_fb(plane, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return tegra_dc_pin(dc, to_tegra_plane_state(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void tegra_plane_cleanup_fb(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			    struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct tegra_dc *dc = to_tegra_dc(state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		tegra_dc_unpin(dc, to_tegra_plane_state(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int tegra_plane_state_add(struct tegra_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			  struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct drm_crtc_state *crtc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct tegra_dc_state *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Propagate errors from allocation or locking failures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (IS_ERR(crtc_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return PTR_ERR(crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* Check plane state for visibility and calculate clipping bounds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	err = drm_atomic_helper_check_plane_state(state, crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 						  0, INT_MAX, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	tegra = to_dc_state(crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	tegra->planes |= WIN_A_ACT_REQ << plane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* assume no swapping of fetched data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (swap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		*swap = BYTE_SWAP_NOSWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	switch (fourcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	case DRM_FORMAT_ARGB4444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		*format = WIN_COLOR_DEPTH_B4G4R4A4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	case DRM_FORMAT_ARGB1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		*format = WIN_COLOR_DEPTH_B5G5R5A1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	case DRM_FORMAT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		*format = WIN_COLOR_DEPTH_B5G6R5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case DRM_FORMAT_RGBA5551:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		*format = WIN_COLOR_DEPTH_A1B5G5R5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	case DRM_FORMAT_ARGB8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		*format = WIN_COLOR_DEPTH_B8G8R8A8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case DRM_FORMAT_ABGR8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		*format = WIN_COLOR_DEPTH_R8G8B8A8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	case DRM_FORMAT_ABGR4444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		*format = WIN_COLOR_DEPTH_R4G4B4A4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	case DRM_FORMAT_ABGR1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		*format = WIN_COLOR_DEPTH_R5G5B5A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	case DRM_FORMAT_BGRA5551:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		*format = WIN_COLOR_DEPTH_AR5G5B5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	case DRM_FORMAT_XRGB1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		*format = WIN_COLOR_DEPTH_B5G5R5X1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	case DRM_FORMAT_RGBX5551:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		*format = WIN_COLOR_DEPTH_X1B5G5R5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	case DRM_FORMAT_XBGR1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		*format = WIN_COLOR_DEPTH_R5G5B5X1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	case DRM_FORMAT_BGRX5551:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		*format = WIN_COLOR_DEPTH_X1R5G5B5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	case DRM_FORMAT_BGR565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		*format = WIN_COLOR_DEPTH_R5G6B5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	case DRM_FORMAT_BGRA8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		*format = WIN_COLOR_DEPTH_A8R8G8B8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	case DRM_FORMAT_RGBA8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		*format = WIN_COLOR_DEPTH_A8B8G8R8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	case DRM_FORMAT_XRGB8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		*format = WIN_COLOR_DEPTH_B8G8R8X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	case DRM_FORMAT_XBGR8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		*format = WIN_COLOR_DEPTH_R8G8B8X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	case DRM_FORMAT_UYVY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		*format = WIN_COLOR_DEPTH_YCbCr422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	case DRM_FORMAT_YUYV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		if (!swap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		*format = WIN_COLOR_DEPTH_YCbCr422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		*swap = BYTE_SWAP_SWAP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	case DRM_FORMAT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		*format = WIN_COLOR_DEPTH_YCbCr420P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	case DRM_FORMAT_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		*format = WIN_COLOR_DEPTH_YCbCr422P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	case WIN_COLOR_DEPTH_YCbCr422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	case WIN_COLOR_DEPTH_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		if (planar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			*planar = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	case WIN_COLOR_DEPTH_YCbCr420P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	case WIN_COLOR_DEPTH_YUV420P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	case WIN_COLOR_DEPTH_YCbCr422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	case WIN_COLOR_DEPTH_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	case WIN_COLOR_DEPTH_YCbCr422R:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	case WIN_COLOR_DEPTH_YUV422R:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	case WIN_COLOR_DEPTH_YCbCr422RA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	case WIN_COLOR_DEPTH_YUV422RA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (planar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			*planar = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (planar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		*planar = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static bool __drm_format_has_alpha(u32 format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	case DRM_FORMAT_ARGB1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	case DRM_FORMAT_RGBA5551:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	case DRM_FORMAT_ABGR8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	case DRM_FORMAT_ARGB8888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int tegra_plane_format_get_alpha(unsigned int opaque,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 					unsigned int *alpha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (tegra_plane_format_is_yuv(opaque, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		*alpha = opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	switch (opaque) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	case WIN_COLOR_DEPTH_B5G5R5X1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		*alpha = WIN_COLOR_DEPTH_B5G5R5A1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	case WIN_COLOR_DEPTH_X1B5G5R5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		*alpha = WIN_COLOR_DEPTH_A1B5G5R5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	case WIN_COLOR_DEPTH_R8G8B8X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		*alpha = WIN_COLOR_DEPTH_R8G8B8A8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	case WIN_COLOR_DEPTH_B8G8R8X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		*alpha = WIN_COLOR_DEPTH_B8G8R8A8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	case WIN_COLOR_DEPTH_B5G6R5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		*alpha = opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)  * This is applicable to Tegra20 and Tegra30 only where the opaque formats can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)  * be emulated using the alpha formats and alpha blending disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int tegra_plane_setup_opacity(struct tegra_plane *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 				     struct tegra_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	unsigned int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	switch (state->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	case WIN_COLOR_DEPTH_B5G5R5A1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	case WIN_COLOR_DEPTH_A1B5G5R5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	case WIN_COLOR_DEPTH_R8G8B8A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	case WIN_COLOR_DEPTH_B8G8R8A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		state->opaque = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		err = tegra_plane_format_get_alpha(state->format, &format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		state->format = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		state->opaque = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int tegra_plane_check_transparency(struct tegra_plane *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 					  struct tegra_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	struct drm_plane_state *old, *plane_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	struct drm_plane *plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	/* check if zpos / transparency changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	if (old->normalized_zpos == state->base.normalized_zpos &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	    to_tegra_plane_state(old)->opaque == state->opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	/* include all sibling planes into this commit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	drm_for_each_plane(plane, tegra->base.dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		struct tegra_plane *p = to_tegra_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		/* skip this plane and planes on different CRTCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		if (p == tegra || p->dc != tegra->dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		plane_state = drm_atomic_get_plane_state(state->base.state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 							 plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		if (IS_ERR(plane_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 			return PTR_ERR(plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 						  struct tegra_plane *other)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	unsigned int index = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	WARN_ON(plane == other);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		if (i == plane->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		if (i == other->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void tegra_plane_update_transparency(struct tegra_plane *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 					    struct tegra_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	struct drm_plane_state *new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	struct drm_plane *plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	for_each_new_plane_in_state(state->base.state, plane, new, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		struct tegra_plane *p = to_tegra_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		unsigned index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		/* skip this plane and planes on different CRTCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		if (p == tegra || p->dc != tegra->dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		index = tegra_plane_get_overlap_index(tegra, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		if (new->fb && __drm_format_has_alpha(new->fb->format->format))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 			state->blending[index].alpha = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 			state->blending[index].alpha = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		if (new->normalized_zpos > state->base.normalized_zpos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 			state->blending[index].top = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 			state->blending[index].top = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		 * Missing framebuffer means that plane is disabled, in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		 * case mark B / C window as top to be able to differentiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		 * windows indices order in regards to zPos for the middle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		 * window X / Y registers programming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		if (!new->fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 			state->blending[index].top = (index == 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int tegra_plane_setup_transparency(struct tegra_plane *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 					  struct tegra_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	struct tegra_plane_state *tegra_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	struct drm_plane_state *new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	struct drm_plane *plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	 * If planes zpos / transparency changed, sibling planes blending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	 * state may require adjustment and in this case they will be included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	 * into this atom commit, otherwise blending state is unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	err = tegra_plane_check_transparency(tegra, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	if (err <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	 * All planes are now in the atomic state, walk them up and update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	 * transparency state for each plane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	drm_for_each_plane(plane, tegra->base.dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		struct tegra_plane *p = to_tegra_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		/* skip planes on different CRTCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 		if (p->dc != tegra->dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		new = drm_atomic_get_new_plane_state(state->base.state, plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		tegra_state = to_tegra_plane_state(new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		 * There is no need to update blending state for the disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		 * plane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		if (new->fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 			tegra_plane_update_transparency(p, tegra_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 				   struct tegra_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	err = tegra_plane_setup_opacity(tegra, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	err = tegra_plane_setup_transparency(tegra, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }