Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef TEGRA_HUB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define TEGRA_HUB_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <drm/drm_plane.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "plane.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct tegra_dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct tegra_windowgroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	unsigned int usecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct host1x_client *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct tegra_shared_plane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct tegra_plane base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	struct tegra_windowgroup *wgrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline struct tegra_shared_plane *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) to_tegra_shared_plane(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	return container_of(plane, struct tegra_shared_plane, base.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct tegra_display_hub_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	unsigned int num_wgrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	bool supports_dsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tegra_display_hub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct drm_private_obj base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	struct host1x_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	struct clk *clk_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct clk *clk_dsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	struct clk *clk_hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	unsigned int num_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct clk **clk_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	const struct tegra_display_hub_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct tegra_windowgroup *wgrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline struct tegra_display_hub *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) to_tegra_display_hub(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	return container_of(client, struct tegra_display_hub, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct tegra_display_hub_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	struct drm_private_state base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	struct tegra_dc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline struct tegra_display_hub_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) to_tegra_display_hub_state(struct drm_private_state *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return container_of(priv, struct tegra_display_hub_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct tegra_dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tegra_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int tegra_display_hub_prepare(struct tegra_display_hub *hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 					    struct tegra_dc *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 					    unsigned int wgrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 					    unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int tegra_display_hub_atomic_check(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 				   struct drm_atomic_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void tegra_display_hub_atomic_commit(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 				     struct drm_atomic_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define  LATENCY_EVENT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define  CURS_SLOTS(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define  WGRP_SLOTS(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif /* TEGRA_HUB_H */