^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/host1x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "dc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "plane.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const u32 tegra_shared_plane_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DRM_FORMAT_ARGB1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DRM_FORMAT_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DRM_FORMAT_RGBA5551,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DRM_FORMAT_ARGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DRM_FORMAT_ABGR8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* new on Tegra114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DRM_FORMAT_ABGR4444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DRM_FORMAT_ABGR1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DRM_FORMAT_BGRA5551,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DRM_FORMAT_XRGB1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DRM_FORMAT_RGBX5551,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DRM_FORMAT_XBGR1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DRM_FORMAT_BGRX5551,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DRM_FORMAT_BGR565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DRM_FORMAT_XRGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DRM_FORMAT_XBGR8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* planar formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DRM_FORMAT_UYVY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DRM_FORMAT_YUYV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DRM_FORMAT_YUV420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DRM_FORMAT_YUV422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const u64 tegra_shared_plane_modifiers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DRM_FORMAT_MOD_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DRM_FORMAT_MOD_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (offset >= 0x500 && offset <= 0x581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) offset = 0x000 + (offset - 0x500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return plane->offset + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (offset >= 0x700 && offset <= 0x73c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) offset = 0x180 + (offset - 0x700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return plane->offset + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (offset >= 0x800 && offset <= 0x83e) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) offset = 0x1c0 + (offset - 0x800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return plane->offset + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return plane->offset + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline u32 tegra_plane_readl(struct tegra_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int tegra_windowgroup_enable(struct tegra_windowgroup *wgrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mutex_lock(&wgrp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (wgrp->usecount == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err = host1x_client_resume(wgrp->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_err(wgrp->parent->dev, "failed to resume: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reset_control_deassert(wgrp->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) wgrp->usecount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mutex_unlock(&wgrp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void tegra_windowgroup_disable(struct tegra_windowgroup *wgrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mutex_lock(&wgrp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (wgrp->usecount == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) err = reset_control_assert(wgrp->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_err("failed to assert reset for window group %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) wgrp->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) host1x_client_suspend(wgrp->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) wgrp->usecount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mutex_unlock(&wgrp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int tegra_display_hub_prepare(struct tegra_display_hub *hub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * XXX Enabling/disabling windowgroups needs to happen when the owner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * display controller is disabled. There's currently no good point at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * which this could be executed, so unconditionally enable all window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * groups for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) for (i = 0; i < hub->soc->num_wgrps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct tegra_windowgroup *wgrp = &hub->wgrps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Skip orphaned window group whose parent DC is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (wgrp->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tegra_windowgroup_enable(wgrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void tegra_display_hub_cleanup(struct tegra_display_hub *hub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * XXX Remove this once window groups can be more fine-grainedly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * enabled and disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < hub->soc->num_wgrps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct tegra_windowgroup *wgrp = &hub->wgrps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Skip orphaned window group whose parent DC is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (wgrp->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tegra_windowgroup_disable(wgrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void tegra_shared_plane_update(struct tegra_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct tegra_dc *dc = plane->dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 mask, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if ((value & mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) usleep_range(100, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void tegra_shared_plane_activate(struct tegra_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct tegra_dc *dc = plane->dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 mask, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if ((value & mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) usleep_range(100, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return tegra_dc_readl(dc, offset) & OWNER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct tegra_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct device *dev = dc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (plane->dc == dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_WARN(dev, "head %u owns window %u but is not attached\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dc->pipe, plane->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int tegra_shared_plane_set_owner(struct tegra_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct tegra_dc *new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tegra_plane_offset(plane, DC_WIN_CORE_WINDOWGROUP_SET_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct tegra_dc *old = plane->dc, *dc = new ? new : old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct device *dev = new ? new->dev : old->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int owner, index = plane->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) value = tegra_dc_readl(dc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) owner = value & OWNER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (new && (owner != OWNER_MASK && owner != new->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_WARN(dev, "window %u owned by head %u\n", index, owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * This seems to happen whenever the head has been disabled with one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * or more windows being active. This is harmless because we'll just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * reassign the window to the new head anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (old && owner == OWNER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_dbg(dev, "window %u not owned by head %u but %u\n", index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) old->pipe, owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) value &= ~OWNER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) value |= OWNER(new->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) value |= OWNER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tegra_dc_writel(dc, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) plane->dc = new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct tegra_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!tegra_dc_owns_shared_plane(dc, plane)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err = tegra_shared_plane_set_owner(plane, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) value |= MODE_FOUR_LINES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) value = SLOTS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* disable watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) value &= ~LATENCY_CTL_MODE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) value |= WATERMARK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* pipe meter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) value = tegra_plane_readl(plane, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) value = PIPE_METER_INT(0) | PIPE_METER_FRAC(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* mempool entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) value = MEMPOOL_ENTRIES(0x331);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) value = tegra_plane_readl(plane, DC_WIN_CORE_IHUB_THREAD_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) value &= ~THREAD_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) value |= THREAD_NUM(plane->base.index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) value |= THREAD_GROUP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tegra_shared_plane_update(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tegra_shared_plane_activate(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void tegra_dc_remove_shared_plane(struct tegra_dc *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct tegra_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tegra_shared_plane_set_owner(plane, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct tegra_shared_plane *tegra = to_tegra_shared_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct tegra_bo_tiling *tiling = &plane_state->tiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct tegra_dc *dc = to_tegra_dc(state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* no need for further checks if the plane is being disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!state->crtc || !state->fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = tegra_plane_format(state->fb->format->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) &plane_state->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) &plane_state->swap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) err = tegra_fb_get_tiling(state->fb, tiling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) !dc->soc->supports_block_linear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DRM_ERROR("hardware doesn't support block linear mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Tegra doesn't support different strides for U and V planes so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * error out if the user tries to display a framebuffer with such a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (state->fb->format->num_planes > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (state->fb->pitches[2] != state->fb->pitches[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DRM_ERROR("unsupported UV-plane configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* XXX scaling is not yet supported, add a check here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) err = tegra_plane_state_add(&tegra->base, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static void tegra_shared_plane_atomic_disable(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct tegra_plane *p = to_tegra_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct tegra_dc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* rien ne va plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!old_state || !old_state->crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dc = to_tegra_dc(old_state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) err = host1x_client_resume(&dc->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(dc->dev, "failed to resume: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * XXX Legacy helpers seem to sometimes call ->atomic_disable() even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * on planes that are already disabled. Make sure we fallback to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * head for this particular state instead of crashing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (WARN_ON(p->dc == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) p->dc = dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) value &= ~WIN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tegra_dc_remove_shared_plane(dc, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) host1x_client_suspend(&dc->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int zpos = plane->state->normalized_zpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct drm_framebuffer *fb = plane->state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct tegra_plane *p = to_tegra_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dma_addr_t base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* rien ne va plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!plane->state->crtc || !plane->state->fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!plane->state->visible) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) tegra_shared_plane_atomic_disable(plane, old_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = host1x_client_resume(&dc->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(dc->dev, "failed to resume: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tegra_dc_assign_shared_plane(dc, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* blending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* bypass scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* disable compression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) base = state->iova[0] + fb->offsets[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) value = V_POSITION(plane->state->crtc_y) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) H_POSITION(plane->state->crtc_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tegra_plane_writel(p, value, DC_WIN_POSITION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) tegra_plane_writel(p, value, DC_WIN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) value = WIN_ENABLE | COLOR_EXPAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) value = V_SIZE(plane->state->crtc_h) | H_SIZE(plane->state->crtc_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) value = PITCH(fb->pitches[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tegra_plane_writel(p, value, DC_WIN_SET_PARAMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) value = OFFSET_X(plane->state->src_y >> 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) OFFSET_Y(plane->state->src_x >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (dc->soc->supports_block_linear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long height = state->tiling.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) switch (state->tiling.mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case TEGRA_BO_TILING_MODE_PITCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DC_WINBUF_SURFACE_KIND_PITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* XXX not supported on Tegra186 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case TEGRA_BO_TILING_MODE_TILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) value = DC_WINBUF_SURFACE_KIND_TILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case TEGRA_BO_TILING_MODE_BLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DC_WINBUF_SURFACE_KIND_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* disable gamut CSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) value &= ~CONTROL_CSC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) host1x_client_suspend(&dc->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .prepare_fb = tegra_plane_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .cleanup_fb = tegra_plane_cleanup_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .atomic_check = tegra_shared_plane_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .atomic_update = tegra_shared_plane_atomic_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .atomic_disable = tegra_shared_plane_atomic_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct tegra_dc *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned int wgrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct tegra_display_hub *hub = tegra->hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* planes can be assigned to arbitrary CRTCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int possible_crtcs = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct tegra_shared_plane *plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned int num_formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) const u64 *modifiers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct drm_plane *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) const u32 *formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) plane = kzalloc(sizeof(*plane), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) plane->base.offset = 0x0a00 + 0x0300 * index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) plane->base.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) plane->wgrp = &hub->wgrps[wgrp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) plane->wgrp->parent = &dc->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) p = &plane->base.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) num_formats = ARRAY_SIZE(tegra_shared_plane_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) formats = tegra_shared_plane_formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) modifiers = tegra_shared_plane_modifiers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) err = drm_universal_plane_init(drm, p, possible_crtcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) &tegra_plane_funcs, formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) num_formats, modifiers, type, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) kfree(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) drm_plane_create_zpos_property(p, 0, 0, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct drm_private_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) tegra_display_hub_duplicate_state(struct drm_private_obj *obj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct tegra_display_hub_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return &state->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void tegra_display_hub_destroy_state(struct drm_private_obj *obj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct drm_private_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct tegra_display_hub_state *hub_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) to_tegra_display_hub_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) kfree(hub_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const struct drm_private_state_funcs tegra_display_hub_state_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .atomic_duplicate_state = tegra_display_hub_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .atomic_destroy_state = tegra_display_hub_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct tegra_display_hub_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tegra_display_hub_get_state(struct tegra_display_hub *hub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct drm_atomic_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct drm_private_state *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) priv = drm_atomic_get_private_obj_state(state, &hub->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (IS_ERR(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ERR_CAST(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return to_tegra_display_hub_state(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int tegra_display_hub_atomic_check(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct drm_atomic_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct tegra_display_hub_state *hub_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct drm_crtc_state *old, *new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct drm_crtc *crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!tegra->hub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) hub_state = tegra_display_hub_get_state(tegra->hub, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (IS_ERR(hub_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return PTR_ERR(hub_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * The display hub display clock needs to be fed by the display clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * with the highest frequency to ensure proper functioning of all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * displays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Note that this isn't used before Tegra186, but it doesn't hurt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * conditionalizing it would make the code less clean.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) for_each_oldnew_crtc_in_state(state, crtc, old, new, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct tegra_dc_state *dc = to_dc_state(new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (new->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!hub_state->clk || dc->pclk > hub_state->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hub_state->dc = to_tegra_dc(dc->base.crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) hub_state->clk = hub_state->dc->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hub_state->rate = dc->pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void tegra_display_hub_update(struct tegra_dc *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) err = host1x_client_resume(&dc->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_err(dc->dev, "failed to resume: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) value &= ~LATENCY_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) value = CURS_SLOTS(1) | WGRP_SLOTS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) host1x_client_suspend(&dc->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void tegra_display_hub_atomic_commit(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct drm_atomic_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct tegra_display_hub *hub = tegra->hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct tegra_display_hub_state *hub_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct device *dev = hub->client.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) hub_state = to_tegra_display_hub_state(hub->base.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (hub_state->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) err = clk_set_rate(hub_state->clk, hub_state->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_err(dev, "failed to set rate of %pC to %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) hub_state->clk, hub_state->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err = clk_set_parent(hub->clk_disp, hub_state->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_err(dev, "failed to set parent of %pC to %pC: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) hub->clk_disp, hub_state->clk, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (hub_state->dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) tegra_display_hub_update(hub_state->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int tegra_display_hub_init(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct tegra_display_hub *hub = to_tegra_display_hub(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct drm_device *drm = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct tegra_display_hub_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) drm_atomic_private_obj_init(drm, &hub->base, &state->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) &tegra_display_hub_state_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) tegra->hub = hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int tegra_display_hub_exit(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct drm_device *drm = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) drm_atomic_private_obj_fini(&tegra->hub->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tegra->hub = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int tegra_display_hub_runtime_suspend(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct tegra_display_hub *hub = to_tegra_display_hub(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct device *dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned int i = hub->num_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) err = reset_control_assert(hub->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) clk_disable_unprepare(hub->clk_heads[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) clk_disable_unprepare(hub->clk_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) clk_disable_unprepare(hub->clk_dsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) clk_disable_unprepare(hub->clk_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int tegra_display_hub_runtime_resume(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct tegra_display_hub *hub = to_tegra_display_hub(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct device *dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) err = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(dev, "failed to get runtime PM: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) err = clk_prepare_enable(hub->clk_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) goto put_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err = clk_prepare_enable(hub->clk_dsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) goto disable_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) err = clk_prepare_enable(hub->clk_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) goto disable_dsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) for (i = 0; i < hub->num_heads; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) err = clk_prepare_enable(hub->clk_heads[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto disable_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) err = reset_control_deassert(hub->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto disable_heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) disable_heads:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) clk_disable_unprepare(hub->clk_heads[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) clk_disable_unprepare(hub->clk_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) disable_dsc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) clk_disable_unprepare(hub->clk_dsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) disable_disp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) clk_disable_unprepare(hub->clk_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) put_rpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct host1x_client_ops tegra_display_hub_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .init = tegra_display_hub_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .exit = tegra_display_hub_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .suspend = tegra_display_hub_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .resume = tegra_display_hub_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int tegra_display_hub_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct device_node *child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct tegra_display_hub *hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) hub = devm_kzalloc(&pdev->dev, sizeof(*hub), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!hub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) hub->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) hub->clk_disp = devm_clk_get(&pdev->dev, "disp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (IS_ERR(hub->clk_disp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) err = PTR_ERR(hub->clk_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (hub->soc->supports_dsc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (IS_ERR(hub->clk_dsc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) err = PTR_ERR(hub->clk_dsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) hub->clk_hub = devm_clk_get(&pdev->dev, "hub");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (IS_ERR(hub->clk_hub)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) err = PTR_ERR(hub->clk_hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) hub->rst = devm_reset_control_get(&pdev->dev, "misc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (IS_ERR(hub->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) err = PTR_ERR(hub->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) hub->wgrps = devm_kcalloc(&pdev->dev, hub->soc->num_wgrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) sizeof(*hub->wgrps), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!hub->wgrps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) for (i = 0; i < hub->soc->num_wgrps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct tegra_windowgroup *wgrp = &hub->wgrps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) char id[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) snprintf(id, sizeof(id), "wgrp%u", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) mutex_init(&wgrp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) wgrp->usecount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) wgrp->index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) wgrp->rst = devm_reset_control_get(&pdev->dev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (IS_ERR(wgrp->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return PTR_ERR(wgrp->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) err = reset_control_assert(wgrp->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) hub->num_heads = of_get_child_count(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) hub->clk_heads = devm_kcalloc(&pdev->dev, hub->num_heads, sizeof(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!hub->clk_heads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) for (i = 0; i < hub->num_heads; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) child = of_get_next_child(pdev->dev.of_node, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_err(&pdev->dev, "failed to find node for head %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) clk = devm_get_clk_from_child(&pdev->dev, child, "dc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev_err(&pdev->dev, "failed to get clock for head %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) hub->clk_heads[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* XXX: enable clock across reset? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) err = reset_control_assert(hub->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) platform_set_drvdata(pdev, hub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) INIT_LIST_HEAD(&hub->client.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) hub->client.ops = &tegra_display_hub_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) hub->client.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) err = host1x_client_register(&hub->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_err(&pdev->dev, "failed to register host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) err = devm_of_platform_populate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) host1x_client_unregister(&hub->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int tegra_display_hub_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct tegra_display_hub *hub = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) err = host1x_client_unregister(&hub->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) for (i = 0; i < hub->soc->num_wgrps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct tegra_windowgroup *wgrp = &hub->wgrps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mutex_destroy(&wgrp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const struct tegra_display_hub_soc tegra186_display_hub = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .num_wgrps = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .supports_dsc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const struct tegra_display_hub_soc tegra194_display_hub = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .num_wgrps = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .supports_dsc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const struct of_device_id tegra_display_hub_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .compatible = "nvidia,tegra194-display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .data = &tegra194_display_hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .compatible = "nvidia,tegra186-display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .data = &tegra186_display_hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) MODULE_DEVICE_TABLE(of, tegra_display_hub_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct platform_driver tegra_display_hub_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .name = "tegra-display-hub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .of_match_table = tegra_display_hub_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .probe = tegra_display_hub_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .remove = tegra_display_hub_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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