Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012 Avionic Design GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef TEGRA_HDMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define TEGRA_HDMI_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define HDMI_CTXSW						0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define HDMI_NV_PDISP_SOR_STATE0				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define SOR_STATE_UPDATE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define HDMI_NV_PDISP_SOR_STATE1				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SOR_STATE_ASY_ORMODE_NORMAL     (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SOR_STATE_ATTACHED              (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HDMI_NV_PDISP_SOR_STATE2				0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SOR_STATE_ASY_OWNER_NONE         (0 <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SOR_STATE_ASY_OWNER_HEAD0        (1 <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SOR_STATE_ASY_SUBOWNER_NONE      (0 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SOR_STATE_ASY_SUBOWNER_SUBHEAD0  (1 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SOR_STATE_ASY_SUBOWNER_SUBHEAD1  (2 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SOR_STATE_ASY_SUBOWNER_BOTH      (3 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SOR_STATE_ASY_CRCMODE_ACTIVE     (0 <<  6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SOR_STATE_ASY_CRCMODE_COMPLETE   (1 <<  6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 <<  6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SOR_STATE_ASY_PROTOCOL_CUSTOM        (15 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SOR_STATE_ASY_HSYNCPOL_POS       (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SOR_STATE_ASY_HSYNCPOL_NEG       (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SOR_STATE_ASY_VSYNCPOL_POS       (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SOR_STATE_ASY_VSYNCPOL_NEG       (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SOR_STATE_ASY_DEPOL_POS          (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SOR_STATE_ASY_DEPOL_NEG          (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HDMI_NV_PDISP_RG_HDCP_AN_MSB				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HDMI_NV_PDISP_RG_HDCP_AN_LSB				0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HDMI_NV_PDISP_RG_HDCP_CN_MSB				0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HDMI_NV_PDISP_RG_HDCP_CN_LSB				0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB				0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB				0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB				0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB				0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB				0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB				0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB				0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HDMI_NV_PDISP_RG_HDCP_CTRL				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HDMI_NV_PDISP_RG_HDCP_CMODE				0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB			0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB			0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2			0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1			0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define HDMI_NV_PDISP_RG_HDCP_RI				0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define HDMI_NV_PDISP_RG_HDCP_CS_MSB				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HDMI_NV_PDISP_RG_HDCP_CS_LSB				0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0				0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0			0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1				0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2				0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL			0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL			0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER			0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH		0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define INFOFRAME_CTRL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define INFOFRAME_HEADER_TYPE(x)    (((x) & 0xff) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define INFOFRAME_HEADER_LEN(x)     (((x) & 0x0f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL				0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define GENERIC_CTRL_ENABLE (1 <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GENERIC_CTRL_OTHER  (1 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GENERIC_CTRL_SINGLE (1 <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define GENERIC_CTRL_HBLANK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GENERIC_CTRL_AUDIO  (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS			0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW			0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH		0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW			0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW			0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW			0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HDMI_NV_PDISP_HDMI_ACR_CTRL				0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW			0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH		0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH		0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW			0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW			0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH		0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW			0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH		0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW			0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH		0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ACR_SUBPACK_N(x)   (((x) & 0xffffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ACR_ENABLE         (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HDMI_NV_PDISP_HDMI_CTRL					0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HDMI_CTRL_REKEY(x)         (((x) & 0x7f) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HDMI_CTRL_ENABLE           (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT			0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW				0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VSYNC_WINDOW_END(x)   (((x) & 0x3ff) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VSYNC_WINDOW_ENABLE   (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HDMI_NV_PDISP_HDMI_GCP_CTRL				0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HDMI_NV_PDISP_HDMI_GCP_STATUS				0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK				0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1			0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2			0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HDMI_NV_PDISP_HDMI_EMU0					0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HDMI_NV_PDISP_HDMI_EMU1					0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HDMI_NV_PDISP_HDMI_EMU1_RDATA				0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HDMI_NV_PDISP_HDMI_SPARE				0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SPARE_HW_CTS           (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SPARE_FORCE_SW_CTS     (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1			0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2			0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL			0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HDMI_NV_PDISP_SOR_CAP					0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HDMI_NV_PDISP_SOR_PWR					0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SOR_PWR_NORMAL_STATE_PD     (0 <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SOR_PWR_NORMAL_STATE_PU     (1 <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SOR_PWR_NORMAL_START_NORMAL (0 <<  1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SOR_PWR_NORMAL_START_ALT    (1 <<  1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SOR_PWR_SAFE_STATE_PD       (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SOR_PWR_SAFE_STATE_PU       (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SOR_PWR_SETTING_NEW_DONE    (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HDMI_NV_PDISP_SOR_TEST					0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HDMI_NV_PDISP_SOR_PLL0					0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SOR_PLL_PWR            (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SOR_PLL_PDBG           (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SOR_PLL_VCAPD          (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SOR_PLL_PDPORT         (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SOR_PLL_RESISTORSEL    (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SOR_PLL_PULLDOWN       (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SOR_PLL_VCOCAP(x)      (((x) & 0xf) <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SOR_PLL_BG_V17_S(x)    (((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SOR_PLL_FILTER(x)      (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SOR_PLL_ICHPMP(x)      (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HDMI_NV_PDISP_SOR_PLL1					0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SOR_PLL_TMDS_TERMADJ(x)  (((x) & 0xf) <<  9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SOR_PLL_LOADADJ(x)       (((x) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SOR_PLL_PE_EN            (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SOR_PLL_HALF_FULL_PE     (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SOR_PLL_S_D_PIN_PE       (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HDMI_NV_PDISP_SOR_PLL2					0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HDMI_NV_PDISP_SOR_CSTM					0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SOR_CSTM_PLLDIV (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SOR_CSTM_LVDS_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SOR_CSTM_MODE_LVDS (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SOR_CSTM_MODE_TMDS (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SOR_CSTM_MODE_MASK (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HDMI_NV_PDISP_SOR_LVDS					0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HDMI_NV_PDISP_SOR_CRCA					0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HDMI_NV_PDISP_SOR_CRCB					0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HDMI_NV_PDISP_SOR_BLANK					0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HDMI_NV_PDISP_SOR_SEQ_CTL				0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SOR_SEQ_PU_PC(x)     (((x) & 0xf) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SOR_SEQ_PD_PC(x)     (((x) & 0xf) <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SOR_SEQ_PC(x)        (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SOR_SEQ_STATUS       (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SOR_SEQ_SWITCH       (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HDMI_NV_PDISP_SOR_SEQ_INST(x)				(0x60 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SOR_SEQ_INST_WAIT_TIME(x)     (((x) & 0x3ff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SOR_SEQ_INST_HALT             (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SOR_SEQ_INST_PIN_A_LOW        (0 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SOR_SEQ_INST_PIN_A_HIGH       (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SOR_SEQ_INST_PIN_B_LOW        (0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SOR_SEQ_INST_PIN_B_HIGH       (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HDMI_NV_PDISP_SOR_VCRCA0				0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HDMI_NV_PDISP_SOR_VCRCA1				0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HDMI_NV_PDISP_SOR_CCRCA0				0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HDMI_NV_PDISP_SOR_CCRCA1				0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HDMI_NV_PDISP_SOR_EDATAA0				0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HDMI_NV_PDISP_SOR_EDATAA1				0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HDMI_NV_PDISP_SOR_COUNTA0				0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HDMI_NV_PDISP_SOR_COUNTA1				0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HDMI_NV_PDISP_SOR_DEBUGA0				0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HDMI_NV_PDISP_SOR_DEBUGA1				0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HDMI_NV_PDISP_SOR_TRIG					0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HDMI_NV_PDISP_SOR_MSCHECK				0x7d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT			0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DRIVE_CURRENT_LANE0(x)      (((x) & 0x3f) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DRIVE_CURRENT_LANE1(x)      (((x) & 0x3f) <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DRIVE_CURRENT_LANE2(x)      (((x) & 0x3f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DRIVE_CURRENT_LANE3(x)      (((x) & 0x3f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DRIVE_CURRENT_1_500_mA  0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DRIVE_CURRENT_1_875_mA  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DRIVE_CURRENT_2_250_mA  0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DRIVE_CURRENT_2_625_mA  0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DRIVE_CURRENT_3_000_mA  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DRIVE_CURRENT_3_375_mA  0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DRIVE_CURRENT_3_750_mA  0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DRIVE_CURRENT_4_125_mA  0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DRIVE_CURRENT_4_500_mA  0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DRIVE_CURRENT_4_875_mA  0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DRIVE_CURRENT_5_250_mA  0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DRIVE_CURRENT_5_625_mA  0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DRIVE_CURRENT_6_000_mA  0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRIVE_CURRENT_6_375_mA  0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRIVE_CURRENT_6_750_mA  0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRIVE_CURRENT_7_125_mA  0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRIVE_CURRENT_7_500_mA  0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRIVE_CURRENT_7_875_mA  0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DRIVE_CURRENT_8_250_mA  0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DRIVE_CURRENT_8_625_mA  0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DRIVE_CURRENT_9_000_mA  0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DRIVE_CURRENT_9_375_mA  0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DRIVE_CURRENT_9_750_mA  0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DRIVE_CURRENT_10_125_mA 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRIVE_CURRENT_10_500_mA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DRIVE_CURRENT_10_875_mA 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DRIVE_CURRENT_11_250_mA 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DRIVE_CURRENT_11_625_mA 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DRIVE_CURRENT_12_000_mA 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DRIVE_CURRENT_12_375_mA 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRIVE_CURRENT_12_750_mA 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRIVE_CURRENT_13_125_mA 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DRIVE_CURRENT_13_500_mA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRIVE_CURRENT_13_875_mA 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DRIVE_CURRENT_14_250_mA 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DRIVE_CURRENT_14_625_mA 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DRIVE_CURRENT_15_000_mA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DRIVE_CURRENT_15_375_mA 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DRIVE_CURRENT_15_750_mA 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRIVE_CURRENT_16_125_mA 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DRIVE_CURRENT_16_500_mA 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DRIVE_CURRENT_16_875_mA 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DRIVE_CURRENT_17_250_mA 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DRIVE_CURRENT_17_625_mA 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DRIVE_CURRENT_18_000_mA 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DRIVE_CURRENT_18_375_mA 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DRIVE_CURRENT_18_750_mA 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRIVE_CURRENT_19_125_mA 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DRIVE_CURRENT_19_500_mA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DRIVE_CURRENT_19_875_mA 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DRIVE_CURRENT_20_250_mA 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DRIVE_CURRENT_20_625_mA 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DRIVE_CURRENT_21_000_mA 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DRIVE_CURRENT_21_375_mA 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRIVE_CURRENT_21_750_mA 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRIVE_CURRENT_22_125_mA 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DRIVE_CURRENT_22_500_mA 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DRIVE_CURRENT_22_875_mA 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DRIVE_CURRENT_23_250_mA 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRIVE_CURRENT_23_625_mA 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRIVE_CURRENT_24_000_mA 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRIVE_CURRENT_24_375_mA 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRIVE_CURRENT_24_750_mA 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRIVE_CURRENT_0_000_mA_T114 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRIVE_CURRENT_0_400_mA_T114 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRIVE_CURRENT_0_800_mA_T114 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRIVE_CURRENT_1_200_mA_T114 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DRIVE_CURRENT_1_600_mA_T114 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DRIVE_CURRENT_2_000_mA_T114 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRIVE_CURRENT_2_400_mA_T114 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DRIVE_CURRENT_2_800_mA_T114 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DRIVE_CURRENT_3_200_mA_T114 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DRIVE_CURRENT_3_600_mA_T114 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DRIVE_CURRENT_4_000_mA_T114 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DRIVE_CURRENT_4_400_mA_T114 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DRIVE_CURRENT_4_800_mA_T114 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DRIVE_CURRENT_5_200_mA_T114 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DRIVE_CURRENT_5_600_mA_T114 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DRIVE_CURRENT_6_000_mA_T114 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DRIVE_CURRENT_6_400_mA_T114 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DRIVE_CURRENT_6_800_mA_T114 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DRIVE_CURRENT_7_200_mA_T114 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DRIVE_CURRENT_7_600_mA_T114 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DRIVE_CURRENT_8_000_mA_T114 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRIVE_CURRENT_8_400_mA_T114 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DRIVE_CURRENT_8_800_mA_T114 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DRIVE_CURRENT_9_200_mA_T114 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DRIVE_CURRENT_9_600_mA_T114 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DRIVE_CURRENT_10_000_mA_T114 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DRIVE_CURRENT_10_400_mA_T114 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DRIVE_CURRENT_10_800_mA_T114 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DRIVE_CURRENT_11_200_mA_T114 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DRIVE_CURRENT_11_600_mA_T114 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DRIVE_CURRENT_12_000_mA_T114 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DRIVE_CURRENT_12_400_mA_T114 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DRIVE_CURRENT_12_800_mA_T114 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DRIVE_CURRENT_13_200_mA_T114 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DRIVE_CURRENT_13_600_mA_T114 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DRIVE_CURRENT_14_000_mA_T114 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DRIVE_CURRENT_14_400_mA_T114 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DRIVE_CURRENT_14_800_mA_T114 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DRIVE_CURRENT_15_200_mA_T114 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DRIVE_CURRENT_15_600_mA_T114 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DRIVE_CURRENT_16_000_mA_T114 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DRIVE_CURRENT_16_400_mA_T114 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DRIVE_CURRENT_16_800_mA_T114 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DRIVE_CURRENT_17_200_mA_T114 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DRIVE_CURRENT_17_600_mA_T114 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DRIVE_CURRENT_18_000_mA_T114 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DRIVE_CURRENT_18_400_mA_T114 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DRIVE_CURRENT_18_800_mA_T114 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DRIVE_CURRENT_19_200_mA_T114 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DRIVE_CURRENT_19_600_mA_T114 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DRIVE_CURRENT_20_000_mA_T114 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DRIVE_CURRENT_20_400_mA_T114 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DRIVE_CURRENT_20_800_mA_T114 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DRIVE_CURRENT_21_200_mA_T114 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DRIVE_CURRENT_21_600_mA_T114 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DRIVE_CURRENT_22_000_mA_T114 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DRIVE_CURRENT_22_400_mA_T114 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DRIVE_CURRENT_22_800_mA_T114 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DRIVE_CURRENT_23_200_mA_T114 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DRIVE_CURRENT_23_600_mA_T114 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DRIVE_CURRENT_24_000_mA_T114 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DRIVE_CURRENT_24_400_mA_T114 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DRIVE_CURRENT_24_800_mA_T114 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DRIVE_CURRENT_25_200_mA_T114 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DRIVE_CURRENT_25_400_mA_T114 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DRIVE_CURRENT_25_800_mA_T114 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DRIVE_CURRENT_26_200_mA_T114 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define DRIVE_CURRENT_26_600_mA_T114 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define DRIVE_CURRENT_27_000_mA_T114 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DRIVE_CURRENT_27_400_mA_T114 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DRIVE_CURRENT_27_800_mA_T114 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DRIVE_CURRENT_28_200_mA_T114 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define HDMI_NV_PDISP_AUDIO_DEBUG0				0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define HDMI_NV_PDISP_AUDIO_DEBUG1				0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define HDMI_NV_PDISP_AUDIO_DEBUG2				0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define HDMI_NV_PDISP_AUDIO_FS(x)				(0x82 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define AUDIO_FS_LOW(x)  (((x) & 0xfff) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH				0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define HDMI_NV_PDISP_AUDIO_THRESHOLD				0x8a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define HDMI_NV_PDISP_AUDIO_CNTRL0				0x8b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define AUDIO_CNTRL0_ERROR_TOLERANCE(x)  (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define AUDIO_CNTRL0_SOURCE_SELECT_AUTO  (0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define AUDIO_CNTRL0_SOURCE_SELECT_HDAL  (2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define HDMI_NV_PDISP_AUDIO_N					0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define AUDIO_N_VALUE(x)           (((x) & 0xfffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define AUDIO_N_RESETF             (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define AUDIO_N_GENERATE_NORMAL    (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING			0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define HDMI_NV_PDISP_SOR_REFCLK				0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SOR_REFCLK_DIV_INT(x)  (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define HDMI_NV_PDISP_CRC_CONTROL				0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define HDMI_NV_PDISP_INPUT_CONTROL				0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define HDMI_SRC_DISPLAYA       (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define HDMI_SRC_DISPLAYB       (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define ARM_VIDEO_RANGE_FULL    (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define ARM_VIDEO_RANGE_LIMITED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define HDMI_NV_PDISP_SCRATCH					0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define HDMI_NV_PDISP_PE_CURRENT				0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PE_CURRENT0(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PE_CURRENT1(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PE_CURRENT2(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PE_CURRENT3(x) (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PE_CURRENT_0_0_mA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PE_CURRENT_0_5_mA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PE_CURRENT_1_0_mA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PE_CURRENT_1_5_mA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PE_CURRENT_2_0_mA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PE_CURRENT_2_5_mA 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PE_CURRENT_3_0_mA 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PE_CURRENT_3_5_mA 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PE_CURRENT_4_0_mA 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PE_CURRENT_4_5_mA 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PE_CURRENT_5_0_mA 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PE_CURRENT_5_5_mA 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PE_CURRENT_6_0_mA 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PE_CURRENT_6_5_mA 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PE_CURRENT_7_0_mA 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PE_CURRENT_7_5_mA 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PE_CURRENT_0_mA_T114 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PE_CURRENT_1_mA_T114 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PE_CURRENT_2_mA_T114 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PE_CURRENT_3_mA_T114 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define PE_CURRENT_4_mA_T114 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PE_CURRENT_5_mA_T114 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PE_CURRENT_6_mA_T114 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PE_CURRENT_7_mA_T114 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PE_CURRENT_8_mA_T114 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PE_CURRENT_9_mA_T114 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PE_CURRENT_10_mA_T114 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PE_CURRENT_11_mA_T114 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PE_CURRENT_12_mA_T114 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PE_CURRENT_13_mA_T114 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PE_CURRENT_14_mA_T114 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PE_CURRENT_15_mA_T114 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define HDMI_NV_PDISP_KEY_CTRL					0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define HDMI_NV_PDISP_KEY_DEBUG0				0x9b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define HDMI_NV_PDISP_KEY_DEBUG1				0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define HDMI_NV_PDISP_KEY_DEBUG2				0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define HDMI_NV_PDISP_KEY_HDCP_KEY_0				0x9e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define HDMI_NV_PDISP_KEY_HDCP_KEY_1				0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define HDMI_NV_PDISP_KEY_HDCP_KEY_2				0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define HDMI_NV_PDISP_KEY_HDCP_KEY_3				0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG				0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define HDMI_NV_PDISP_KEY_SKEY_INDEX				0xa3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0				0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define  SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO	(0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define  SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define  SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL	(2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define  SOR_AUDIO_CNTRL0_INJECT_NULLSMPL	(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0				0xae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define  SOR_AUDIO_SPARE0_HBR_ENABLE		(1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0		0xba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define  SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID	(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define  SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1		0xbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR			0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE			0xbd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define  SOR_AUDIO_HDA_PRESENSE_VALID		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define  SOR_AUDIO_HDA_PRESENSE_PRESENT		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320    0xbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441    0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882    0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764    0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480    0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960    0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920    0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define HDMI_NV_PDISP_INT_STATUS			0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define  INT_SCRATCH		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define  INT_CP_REQUEST		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define  INT_CODEC_SCRATCH1	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define  INT_CODEC_SCRATCH0	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define HDMI_NV_PDISP_INT_MASK				0xcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define HDMI_NV_PDISP_INT_ENABLE			0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT		0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) <<  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PEAK_CURRENT_0_000_mA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define PEAK_CURRENT_0_200_mA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define PEAK_CURRENT_0_400_mA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define PEAK_CURRENT_0_600_mA 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define PEAK_CURRENT_0_800_mA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define PEAK_CURRENT_1_000_mA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define PEAK_CURRENT_1_200_mA 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define PEAK_CURRENT_1_400_mA 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define PEAK_CURRENT_1_600_mA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define PEAK_CURRENT_1_800_mA 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define PEAK_CURRENT_2_000_mA 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define PEAK_CURRENT_2_200_mA 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define PEAK_CURRENT_2_400_mA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define PEAK_CURRENT_2_600_mA 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define PEAK_CURRENT_2_800_mA 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define PEAK_CURRENT_3_000_mA 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define PEAK_CURRENT_3_200_mA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define PEAK_CURRENT_3_400_mA 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define PEAK_CURRENT_3_600_mA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define PEAK_CURRENT_3_800_mA 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define PEAK_CURRENT_4_000_mA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define PEAK_CURRENT_4_200_mA 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define PEAK_CURRENT_4_400_mA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define PEAK_CURRENT_4_600_mA 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define PEAK_CURRENT_4_800_mA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define PEAK_CURRENT_5_000_mA 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define PEAK_CURRENT_5_200_mA 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define PEAK_CURRENT_5_400_mA 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define PEAK_CURRENT_5_600_mA 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PEAK_CURRENT_5_800_mA 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PEAK_CURRENT_6_000_mA 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define PEAK_CURRENT_6_200_mA 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define PEAK_CURRENT_6_400_mA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define PEAK_CURRENT_6_600_mA 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define PEAK_CURRENT_6_800_mA 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define PEAK_CURRENT_7_000_mA 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define PEAK_CURRENT_7_200_mA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PEAK_CURRENT_7_400_mA 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define PEAK_CURRENT_7_600_mA 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define PEAK_CURRENT_7_800_mA 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define PEAK_CURRENT_8_000_mA 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PEAK_CURRENT_8_200_mA 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define PEAK_CURRENT_8_400_mA 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define PEAK_CURRENT_8_600_mA 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define PEAK_CURRENT_8_800_mA 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define PEAK_CURRENT_9_000_mA 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define PEAK_CURRENT_9_200_mA 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define PEAK_CURRENT_9_400_mA 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HDMI_NV_PDISP_SOR_PAD_CTLS0		0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #endif /* TEGRA_HDMI_H */