^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 Avionic Design GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "hdmi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "dc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HDMI_ELD_BUFFER_SIZE 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct tmds_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 pll0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 pe_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 drive_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 peak_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct tegra_hdmi_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct tmds_config *tmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int num_tmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long fuse_override_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 fuse_override_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) bool has_sor_io_peak_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool has_hda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool has_hbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct tegra_hdmi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct host1x_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct tegra_output output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct regulator *hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct regulator *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct regulator *vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const struct tegra_hdmi_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int audio_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct tegra_hda_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool dvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct drm_info_list *debugfs_files;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline struct tegra_hdmi *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) host1x_client_to_hdmi(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return container_of(client, struct tegra_hdmi, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return container_of(output, struct tegra_hdmi, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HDMI_AUDIOCLK_FREQ 216000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HDMI_REKEY_DEFAULT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) HDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 value = readl(hdmi->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) trace_hdmi_readl(hdmi->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) trace_hdmi_writel(hdmi->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(value, hdmi->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct tegra_hdmi_audio_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int aval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct tmds_config tegra20_tmds_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { /* slow pixel clock modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .pclk = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SOR_PLL_TX_REG_LOAD(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PE_CURRENT1(PE_CURRENT_0_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PE_CURRENT2(PE_CURRENT_0_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PE_CURRENT3(PE_CURRENT_0_0_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { /* high pixel clock modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .pclk = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SOR_PLL_TX_REG_LOAD(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PE_CURRENT1(PE_CURRENT_6_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PE_CURRENT2(PE_CURRENT_6_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PE_CURRENT3(PE_CURRENT_6_0_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct tmds_config tegra30_tmds_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { /* 480p modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .pclk = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SOR_PLL_TX_REG_LOAD(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PE_CURRENT1(PE_CURRENT_0_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PE_CURRENT2(PE_CURRENT_0_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PE_CURRENT3(PE_CURRENT_0_0_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }, { /* 720p modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .pclk = 74250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SOR_PLL_TX_REG_LOAD(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PE_CURRENT1(PE_CURRENT_5_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PE_CURRENT2(PE_CURRENT_5_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PE_CURRENT3(PE_CURRENT_5_0_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }, { /* 1080p modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .pclk = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SOR_PLL_TX_REG_LOAD(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PE_CURRENT1(PE_CURRENT_5_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PE_CURRENT2(PE_CURRENT_5_0_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PE_CURRENT3(PE_CURRENT_5_0_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct tmds_config tegra114_tmds_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { /* 480p/576p / 25.2MHz/27MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .pclk = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PE_CURRENT1(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PE_CURRENT2(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PE_CURRENT3(PE_CURRENT_0_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }, { /* 720p / 74.25MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .pclk = 74250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SOR_PLL_TMDS_TERMADJ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PE_CURRENT1(PE_CURRENT_15_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PE_CURRENT2(PE_CURRENT_15_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PE_CURRENT3(PE_CURRENT_15_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }, { /* 1080p / 148.5MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .pclk = 148500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SOR_PLL_TMDS_TERMADJ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PE_CURRENT1(PE_CURRENT_10_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PE_CURRENT2(PE_CURRENT_10_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PE_CURRENT3(PE_CURRENT_10_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }, { /* 225/297MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .pclk = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) | SOR_PLL_TMDS_TERM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PE_CURRENT1(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PE_CURRENT2(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PE_CURRENT3(PE_CURRENT_0_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct tmds_config tegra124_tmds_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { /* 480p/576p / 25.2MHz/27MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .pclk = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PE_CURRENT1(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PE_CURRENT2(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PE_CURRENT3(PE_CURRENT_0_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }, { /* 720p / 74.25MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .pclk = 74250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SOR_PLL_TMDS_TERMADJ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PE_CURRENT1(PE_CURRENT_15_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PE_CURRENT2(PE_CURRENT_15_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PE_CURRENT3(PE_CURRENT_15_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }, { /* 1080p / 148.5MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .pclk = 148500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SOR_PLL_TMDS_TERMADJ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PE_CURRENT1(PE_CURRENT_10_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PE_CURRENT2(PE_CURRENT_10_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PE_CURRENT3(PE_CURRENT_10_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }, { /* 225/297MHz modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .pclk = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) | SOR_PLL_TMDS_TERM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PE_CURRENT1(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PE_CURRENT2(PE_CURRENT_0_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PE_CURRENT3(PE_CURRENT_0_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .drive_current =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct tegra_hdmi_audio_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) const unsigned int afreq = 128 * audio_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) const unsigned int min_n = afreq / 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const unsigned int max_n = afreq / 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) const unsigned int ideal_n = afreq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int64_t min_err = (uint64_t)-1 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int min_delta = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) memset(config, 0, sizeof(*config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) config->n = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (n = min_n; n <= max_n; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) uint64_t cts_f, aval_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int64_t cts, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* compute aval in 48.16 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) aval_f = ((int64_t)24000000 << 16) * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) do_div(aval_f, afreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* It should round without any rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (aval_f & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Compute cts in 48.16 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cts_f = ((int64_t)pix_clock << 16) * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) do_div(cts_f, afreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Round it to the nearest integer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) delta = abs(n - ideal_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Compute the absolute error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) err = abs((int64_t)cts_f - cts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (err < min_err || (err == min_err && delta < min_delta)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) config->n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) config->cts = cts >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) config->aval = aval_f >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) min_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return config->n != -1 ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const unsigned int freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 32000, 44100, 48000, 88200, 96000, 176400, 192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (i = 0; i < ARRAY_SIZE(freqs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int f = freqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int eight_half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (f > 96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) delta = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else if (f > 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) delta = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) delta = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) value = AUDIO_FS_LOW(eight_half - delta) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) AUDIO_FS_HIGH(eight_half + delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (i = 0; i < ARRAY_SIZE(regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (regs[i].sample_rate == hdmi->format.sample_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tegra_hdmi_writel(hdmi, value, regs[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct tegra_hdmi_audio_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 source, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) switch (hdmi->audio_source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case HDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (hdmi->config->has_hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (hdmi->config->has_hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (hdmi->config->has_hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Tegra30 and later use a slightly modified version of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * layout to accomodate for changes related to supporting HDA as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * audio input source for HDMI. The source select field has moved to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * per block fields remain in the AUDIO_CNTRL0 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (hdmi->config->has_hda) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Inject null samples into the audio FIFO for every frame in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * which the codec did not receive any samples. This applies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * to stereo LPCM only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * XXX: This seems to be a remnant of MCP days when this was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * used to work around issues with monitors not being able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * play back system startup sounds early. It is possibly not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * needed on Linux at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (hdmi->format.channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) value |= source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * On Tegra20, HDA is not a supported audio source and the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * select field is part of the AUDIO_CNTRL0 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) AUDIO_CNTRL0_ERROR_TOLERANCE(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!hdmi->config->has_hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) value |= source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * Advertise support for High Bit-Rate on Tegra114 and later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (hdmi->config->has_hbr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hdmi->pixel_clock, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(hdmi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "cannot set audio to %u Hz at %u Hz pixel clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hdmi->format.sample_rate, hdmi->pixel_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) hdmi->pixel_clock, config.n, config.cts, config.aval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) AUDIO_N_VALUE(config.n - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) value &= ~AUDIO_N_RESETF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (hdmi->config->has_hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tegra_hdmi_write_aval(hdmi, config.aval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tegra_hdmi_setup_audio_fs_tables(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) value &= ~GENERIC_CTRL_AUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) value |= GENERIC_CTRL_AUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) size_t length = drm_eld_size(hdmi->output.connector.eld), i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) for (i = 0; i < length; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * The HDA codec will always report an ELD buffer size of 96 bytes and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * the HDA codec driver will check that each byte read from the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * is valid. Therefore every byte must be written, even if no 96 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * were parsed from EDID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tegra_hdmi_writel(hdmi, i << 8 | 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) for (i = size; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) value = (value << 8) | ptr[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) const u8 *ptr = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) size_t i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) switch (ptr[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case HDMI_INFOFRAME_TYPE_AVI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case HDMI_INFOFRAME_TYPE_AUDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case HDMI_INFOFRAME_TYPE_VENDOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ptr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) value = INFOFRAME_HEADER_TYPE(ptr[0]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) INFOFRAME_HEADER_VERSION(ptr[1]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) INFOFRAME_HEADER_LEN(ptr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) tegra_hdmi_writel(hdmi, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) offset++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Each subpack contains 7 bytes, divided into:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * - subpack_low: bytes 0 - 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for (i = 3, j = 0; i < size; i += 7, j += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) size_t rem = size - i, num = min_t(size_t, rem, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) value = tegra_hdmi_subpack(&ptr[i], num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) tegra_hdmi_writel(hdmi, value, offset++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) num = min_t(size_t, rem - num, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) value = tegra_hdmi_subpack(&ptr[i + 4], num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tegra_hdmi_writel(hdmi, value, offset++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct hdmi_avi_infoframe frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 buffer[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ssize_t err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) &hdmi->output.connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tegra_hdmi_write_infopack(hdmi, buffer, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) value &= ~INFOFRAME_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) value |= INFOFRAME_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct hdmi_audio_infoframe frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u8 buffer[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ssize_t err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) err = hdmi_audio_infoframe_init(&frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) frame.channels = hdmi->format.channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * The audio infoframe has only one set of subpack registers, so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * infoframe needs to be truncated. One set of subpack registers can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * contain 7 bytes. Including the 3 byte header only the first 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * bytes can be programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) value &= ~INFOFRAME_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) value |= INFOFRAME_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct hdmi_vendor_infoframe frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u8 buffer[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ssize_t err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) hdmi_vendor_infoframe_init(&frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) tegra_hdmi_write_infopack(hdmi, buffer, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) value &= ~GENERIC_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) value |= GENERIC_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) const struct tmds_config *tmds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) tegra_hdmi_writel(hdmi, tmds->drive_current,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) value |= hdmi->config->fuse_override_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (hdmi->config->has_sor_io_peak_current)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) tegra_hdmi_writel(hdmi, tmds->peak_current,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static bool tegra_output_is_hdmi(struct tegra_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct edid *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!output->connector.edid_blob_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) edid = (struct edid *)output->connector.edid_blob_ptr->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return drm_detect_hdmi_monitor(edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static enum drm_connector_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct tegra_output *output = connector_to_output(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct tegra_hdmi *hdmi = to_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) enum drm_connector_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) status = tegra_output_connector_detect(connector, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (status == connector_status_connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const struct debugfs_reg32 tegra_hdmi_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) DEBUGFS_REG32(HDMI_CTXSW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct drm_info_node *node = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct tegra_hdmi *hdmi = node->info_ent->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct drm_crtc *crtc = hdmi->output.encoder.crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct drm_device *drm = node->minor->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) drm_modeset_lock_all(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (!crtc || !crtc->state->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) unsigned int offset = tegra_hdmi_regs[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) offset, tegra_hdmi_readl(hdmi, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) drm_modeset_unlock_all(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static struct drm_info_list debugfs_files[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) { "regs", tegra_hdmi_show_regs, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int tegra_hdmi_late_register(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct tegra_output *output = connector_to_output(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned int i, count = ARRAY_SIZE(debugfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct drm_minor *minor = connector->dev->primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct dentry *root = connector->debugfs_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct tegra_hdmi *hdmi = to_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!hdmi->debugfs_files)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) hdmi->debugfs_files[i].data = hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static void tegra_hdmi_early_unregister(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct tegra_output *output = connector_to_output(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct drm_minor *minor = connector->dev->primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) unsigned int count = ARRAY_SIZE(debugfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct tegra_hdmi *hdmi = to_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) kfree(hdmi->debugfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) hdmi->debugfs_files = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .detect = tegra_hdmi_connector_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .destroy = tegra_output_connector_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .late_register = tegra_hdmi_late_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .early_unregister = tegra_hdmi_early_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct tegra_output *output = connector_to_output(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct tegra_hdmi *hdmi = to_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) unsigned long pclk = mode->clock * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) enum drm_mode_status status = MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) long err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) parent = clk_get_parent(hdmi->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) err = clk_round_rate(parent, pclk * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (err <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) status = MODE_NOCLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const struct drm_connector_helper_funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) tegra_hdmi_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .get_modes = tegra_output_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .mode_valid = tegra_hdmi_connector_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct tegra_hdmi *hdmi = to_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * The following accesses registers of the display controller, so make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * sure it's only executed when the output is attached to one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (dc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) value &= ~HDMI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) tegra_dc_commit(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!hdmi->dvi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (hdmi->stereo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) tegra_hdmi_disable_stereo_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) tegra_hdmi_disable_audio_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) tegra_hdmi_disable_avi_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) tegra_hdmi_disable_audio(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) err = host1x_client_suspend(&hdmi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_err(hdmi->dev, "failed to suspend: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct tegra_hdmi *hdmi = to_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) unsigned int pulse_start, div82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int retries = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) err = host1x_client_resume(&hdmi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dev_err(hdmi->dev, "failed to resume: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * is used for interoperability between the HDA codec driver and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * HDMI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) hdmi->pixel_clock = mode->clock * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) h_sync_width = mode->hsync_end - mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) h_back_porch = mode->htotal - mode->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) h_front_porch = mode->hsync_start - mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* power up sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) value &= ~SOR_PLL_PDBG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) value &= ~SOR_PLL_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) tegra_dc_writel(dc, VSYNC_H_POSITION(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) DC_DISP_DISP_TIMING_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) DC_DISP_DISP_COLOR_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* video_preamble uses h_pulse2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pulse_start = 1 + h_sync_width + h_back_porch - 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PULSE_LAST_END_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) VSYNC_WINDOW_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (dc->pipe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) value = HDMI_SRC_DISPLAYB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) value = HDMI_SRC_DISPLAYA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) (mode->vdisplay == 576)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) tegra_hdmi_writel(hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) value | ARM_VIDEO_RANGE_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) HDMI_NV_PDISP_INPUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) tegra_hdmi_writel(hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) value | ARM_VIDEO_RANGE_LIMITED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) HDMI_NV_PDISP_INPUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) hdmi->dvi = !tegra_output_is_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!hdmi->dvi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * Make sure that the audio format has been configured before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * enabling audio, otherwise we may try to divide by zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (hdmi->format.sample_rate > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) err = tegra_hdmi_setup_audio(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) hdmi->dvi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (hdmi->config->has_hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) tegra_hdmi_write_eld(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) rekey = HDMI_REKEY_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) value = HDMI_CTRL_REKEY(rekey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) h_front_porch - rekey - 18) / 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (!hdmi->dvi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) value |= HDMI_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (!hdmi->dvi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) tegra_hdmi_setup_avi_infoframe(hdmi, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) tegra_hdmi_setup_audio_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (hdmi->stereo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) tegra_hdmi_setup_stereo_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* TMDS CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) for (i = 0; i < hdmi->config->num_tmds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) tegra_hdmi_writel(hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) SOR_SEQ_PU_PC(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) SOR_SEQ_PU_PC_ALT(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SOR_SEQ_PD_PC(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) SOR_SEQ_PD_PC_ALT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) HDMI_NV_PDISP_SOR_SEQ_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) value = SOR_SEQ_INST_WAIT_TIME(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) SOR_SEQ_INST_WAIT_UNITS_VSYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) SOR_SEQ_INST_HALT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) SOR_SEQ_INST_PIN_A_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) SOR_SEQ_INST_PIN_B_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) value &= ~SOR_CSTM_ROTCLK(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) value |= SOR_CSTM_ROTCLK(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) value |= SOR_CSTM_PLLDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) value &= ~SOR_CSTM_LVDS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) value &= ~SOR_CSTM_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) value |= SOR_CSTM_MODE_TMDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* start SOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) tegra_hdmi_writel(hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) SOR_PWR_NORMAL_STATE_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) SOR_PWR_NORMAL_START_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) SOR_PWR_SAFE_STATE_PD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) SOR_PWR_SETTING_NEW_TRIGGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) HDMI_NV_PDISP_SOR_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) tegra_hdmi_writel(hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) SOR_PWR_NORMAL_STATE_PU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) SOR_PWR_NORMAL_START_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) SOR_PWR_SAFE_STATE_PD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) SOR_PWR_SETTING_NEW_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) HDMI_NV_PDISP_SOR_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) BUG_ON(--retries < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) } while (value & SOR_PWR_SETTING_NEW_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) value = SOR_STATE_ASY_CRCMODE_COMPLETE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) SOR_STATE_ASY_OWNER_HEAD0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SOR_STATE_ASY_SUBOWNER_BOTH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) SOR_STATE_ASY_DEPOL_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* setup sync polarities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (mode->flags & DRM_MODE_FLAG_PHSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) value |= SOR_STATE_ASY_HSYNCPOL_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (mode->flags & DRM_MODE_FLAG_NHSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) value |= SOR_STATE_ASY_HSYNCPOL_NEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (mode->flags & DRM_MODE_FLAG_PVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) value |= SOR_STATE_ASY_VSYNCPOL_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (mode->flags & DRM_MODE_FLAG_NVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) value |= SOR_STATE_ASY_VSYNCPOL_NEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) HDMI_NV_PDISP_SOR_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) value |= HDMI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) tegra_dc_commit(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (!hdmi->dvi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) tegra_hdmi_enable_avi_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) tegra_hdmi_enable_audio_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) tegra_hdmi_enable_audio(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (hdmi->stereo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) tegra_hdmi_enable_stereo_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* TODO: add HDCP support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) unsigned long pclk = crtc_state->mode.clock * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct tegra_hdmi *hdmi = to_hdmi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pclk, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .disable = tegra_hdmi_encoder_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .enable = tegra_hdmi_encoder_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .atomic_check = tegra_hdmi_encoder_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static int tegra_hdmi_init(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct drm_device *drm = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) hdmi->output.dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) drm_connector_init_with_ddc(drm, &hdmi->output.connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) &tegra_hdmi_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) DRM_MODE_CONNECTOR_HDMIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) hdmi->output.ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) drm_connector_helper_add(&hdmi->output.connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) &tegra_hdmi_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) drm_simple_encoder_init(drm, &hdmi->output.encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) DRM_MODE_ENCODER_TMDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) drm_encoder_helper_add(&hdmi->output.encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) &tegra_hdmi_encoder_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) drm_connector_attach_encoder(&hdmi->output.connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) &hdmi->output.encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) drm_connector_register(&hdmi->output.connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) err = tegra_output_init(drm, &hdmi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_err(client->dev, "failed to initialize output: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) hdmi->output.encoder.possible_crtcs = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) err = regulator_enable(hdmi->hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) err = regulator_enable(hdmi->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) err = regulator_enable(hdmi->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static int tegra_hdmi_exit(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) tegra_output_exit(&hdmi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) regulator_disable(hdmi->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) regulator_disable(hdmi->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) regulator_disable(hdmi->hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct device *dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) err = reset_control_assert(hdmi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) dev_err(dev, "failed to assert reset: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) clk_disable_unprepare(hdmi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static int tegra_hdmi_runtime_resume(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct device *dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) err = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) dev_err(dev, "failed to get runtime PM: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) err = clk_prepare_enable(hdmi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) dev_err(dev, "failed to enable clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) goto put_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) err = reset_control_deassert(hdmi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dev_err(dev, "failed to deassert reset: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) clk_disable_unprepare(hdmi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) put_rpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static const struct host1x_client_ops hdmi_client_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .init = tegra_hdmi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .exit = tegra_hdmi_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .suspend = tegra_hdmi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .resume = tegra_hdmi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static const struct tegra_hdmi_config tegra20_hdmi_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .tmds = tegra20_tmds_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .fuse_override_value = 1 << 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .has_sor_io_peak_current = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .has_hda = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .has_hbr = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static const struct tegra_hdmi_config tegra30_hdmi_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .tmds = tegra30_tmds_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .fuse_override_value = 1 << 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .has_sor_io_peak_current = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .has_hda = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .has_hbr = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static const struct tegra_hdmi_config tegra114_hdmi_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .tmds = tegra114_tmds_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .fuse_override_value = 1 << 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .has_sor_io_peak_current = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .has_hda = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .has_hbr = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static const struct tegra_hdmi_config tegra124_hdmi_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .tmds = tegra124_tmds_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .fuse_override_value = 1 << 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .has_sor_io_peak_current = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .has_hda = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .has_hbr = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static const struct of_device_id tegra_hdmi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static irqreturn_t tegra_hdmi_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct tegra_hdmi *hdmi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (value & INT_CODEC_SCRATCH0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) unsigned int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) tegra_hda_parse_format(format, &hdmi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) err = tegra_hdmi_setup_audio(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) tegra_hdmi_disable_audio_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) tegra_hdmi_disable_audio(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) tegra_hdmi_setup_audio_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) tegra_hdmi_enable_audio_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) tegra_hdmi_enable_audio(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) tegra_hdmi_disable_audio_infoframe(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) tegra_hdmi_disable_audio(hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static int tegra_hdmi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) const char *level = KERN_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct tegra_hdmi *hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (!hdmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) hdmi->config = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) hdmi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) hdmi->audio_source = AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) hdmi->stereo = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) hdmi->dvi = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) hdmi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (IS_ERR(hdmi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) return PTR_ERR(hdmi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (IS_ERR(hdmi->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dev_err(&pdev->dev, "failed to get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return PTR_ERR(hdmi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (IS_ERR(hdmi->clk_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return PTR_ERR(hdmi->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) err = PTR_ERR_OR_ZERO(hdmi->hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) level = KERN_DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) dev_printk(level, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) "failed to get HDMI regulator: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) err = PTR_ERR_OR_ZERO(hdmi->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) level = KERN_DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) dev_printk(level, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) "failed to get PLL regulator: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) err = PTR_ERR_OR_ZERO(hdmi->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) level = KERN_DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) dev_printk(level, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) "failed to get VDD regulator: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) hdmi->output.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) err = tegra_output_probe(&hdmi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (IS_ERR(hdmi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return PTR_ERR(hdmi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) err = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) hdmi->irq = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev_name(hdmi->dev), hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) hdmi->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) platform_set_drvdata(pdev, hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) INIT_LIST_HEAD(&hdmi->client.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) hdmi->client.ops = &hdmi_client_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) hdmi->client.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) err = host1x_client_register(&hdmi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) dev_err(&pdev->dev, "failed to register host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static int tegra_hdmi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) err = host1x_client_unregister(&hdmi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) tegra_output_remove(&hdmi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct platform_driver tegra_hdmi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .name = "tegra-hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .of_match_table = tegra_hdmi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .probe = tegra_hdmi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .remove = tegra_hdmi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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