^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Avionic Design GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/host1x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "gem.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "gr3d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct gr3d_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct gr3d {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct tegra_drm_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct host1x_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk *clk_secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct reset_control *rst_secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct gr3d_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return container_of(client, struct gr3d, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int gr3d_init(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct tegra_drm_client *drm = host1x_to_drm_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct drm_device *dev = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct gr3d *gr3d = to_gr3d(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) gr3d->channel = host1x_channel_request(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (!gr3d->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) client->syncpts[0] = host1x_syncpt_request(client, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (!client->syncpts[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev_err(client->dev, "failed to request syncpoint: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) err = host1x_client_iommu_attach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_err(client->dev, "failed to attach to domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) err = tegra_drm_register_client(dev->dev_private, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dev_err(client->dev, "failed to register client: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) goto detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) detach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) host1x_client_iommu_detach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) host1x_syncpt_free(client->syncpts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) host1x_channel_put(gr3d->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int gr3d_exit(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct tegra_drm_client *drm = host1x_to_drm_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct drm_device *dev = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct gr3d *gr3d = to_gr3d(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) err = tegra_drm_unregister_client(dev->dev_private, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) host1x_client_iommu_detach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) host1x_syncpt_free(client->syncpts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) host1x_channel_put(gr3d->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct host1x_client_ops gr3d_client_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .init = gr3d_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .exit = gr3d_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int gr3d_open_channel(struct tegra_drm_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct tegra_drm_context *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct gr3d *gr3d = to_gr3d(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) context->channel = host1x_channel_get(gr3d->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!context->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void gr3d_close_channel(struct tegra_drm_context *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) host1x_channel_put(context->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct gr3d *gr3d = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) switch (class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case HOST1X_CLASS_HOST1X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (offset == 0x2b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case HOST1X_CLASS_GR3D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (offset >= GR3D_NUM_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (test_bit(offset, gr3d->addr_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct tegra_drm_client_ops gr3d_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .open_channel = gr3d_open_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .close_channel = gr3d_close_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .is_addr_reg = gr3d_is_addr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .submit = tegra_drm_submit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct gr3d_soc tegra20_gr3d_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .version = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct gr3d_soc tegra30_gr3d_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .version = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct gr3d_soc tegra114_gr3d_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .version = 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct of_device_id tegra_gr3d_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_DEVICE_TABLE(of, tegra_gr3d_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const u32 gr3d_addr_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) GR3D_IDX_ATTRIBUTE( 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GR3D_IDX_ATTRIBUTE( 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) GR3D_IDX_ATTRIBUTE( 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) GR3D_IDX_ATTRIBUTE( 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GR3D_IDX_ATTRIBUTE( 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GR3D_IDX_ATTRIBUTE( 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GR3D_IDX_ATTRIBUTE( 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GR3D_IDX_ATTRIBUTE( 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GR3D_IDX_ATTRIBUTE( 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GR3D_IDX_ATTRIBUTE( 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GR3D_IDX_ATTRIBUTE(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GR3D_IDX_ATTRIBUTE(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GR3D_IDX_ATTRIBUTE(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GR3D_IDX_ATTRIBUTE(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GR3D_IDX_ATTRIBUTE(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GR3D_IDX_ATTRIBUTE(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GR3D_IDX_INDEX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GR3D_QR_ZTAG_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GR3D_QR_CTAG_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) GR3D_QR_CZ_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GR3D_TEX_TEX_ADDR( 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) GR3D_TEX_TEX_ADDR( 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) GR3D_TEX_TEX_ADDR( 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) GR3D_TEX_TEX_ADDR( 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) GR3D_TEX_TEX_ADDR( 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GR3D_TEX_TEX_ADDR( 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GR3D_TEX_TEX_ADDR( 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) GR3D_TEX_TEX_ADDR( 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) GR3D_TEX_TEX_ADDR( 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GR3D_TEX_TEX_ADDR( 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) GR3D_TEX_TEX_ADDR(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GR3D_TEX_TEX_ADDR(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GR3D_TEX_TEX_ADDR(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) GR3D_TEX_TEX_ADDR(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) GR3D_TEX_TEX_ADDR(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) GR3D_TEX_TEX_ADDR(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) GR3D_DW_MEMORY_OUTPUT_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) GR3D_GLOBAL_SURFADDR( 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) GR3D_GLOBAL_SURFADDR( 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) GR3D_GLOBAL_SURFADDR( 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) GR3D_GLOBAL_SURFADDR( 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) GR3D_GLOBAL_SURFADDR( 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) GR3D_GLOBAL_SURFADDR( 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) GR3D_GLOBAL_SURFADDR( 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GR3D_GLOBAL_SURFADDR( 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) GR3D_GLOBAL_SURFADDR( 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GR3D_GLOBAL_SURFADDR( 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) GR3D_GLOBAL_SURFADDR(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) GR3D_GLOBAL_SURFADDR(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) GR3D_GLOBAL_SURFADDR(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) GR3D_GLOBAL_SURFADDR(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) GR3D_GLOBAL_SURFADDR(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) GR3D_GLOBAL_SURFADDR(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GR3D_GLOBAL_SPILLSURFADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) GR3D_GLOBAL_SURFOVERADDR( 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GR3D_GLOBAL_SURFOVERADDR( 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GR3D_GLOBAL_SURFOVERADDR( 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GR3D_GLOBAL_SURFOVERADDR( 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GR3D_GLOBAL_SURFOVERADDR( 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GR3D_GLOBAL_SURFOVERADDR( 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GR3D_GLOBAL_SURFOVERADDR( 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GR3D_GLOBAL_SURFOVERADDR( 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GR3D_GLOBAL_SURFOVERADDR( 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GR3D_GLOBAL_SURFOVERADDR( 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GR3D_GLOBAL_SURFOVERADDR(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GR3D_GLOBAL_SURFOVERADDR(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GR3D_GLOBAL_SURFOVERADDR(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) GR3D_GLOBAL_SURFOVERADDR(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GR3D_GLOBAL_SURFOVERADDR(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GR3D_GLOBAL_SURFOVERADDR(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GR3D_GLOBAL_SAMP01SURFADDR( 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) GR3D_GLOBAL_SAMP01SURFADDR( 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GR3D_GLOBAL_SAMP01SURFADDR( 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) GR3D_GLOBAL_SAMP01SURFADDR( 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GR3D_GLOBAL_SAMP01SURFADDR( 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) GR3D_GLOBAL_SAMP01SURFADDR( 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GR3D_GLOBAL_SAMP01SURFADDR( 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) GR3D_GLOBAL_SAMP01SURFADDR( 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) GR3D_GLOBAL_SAMP01SURFADDR( 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) GR3D_GLOBAL_SAMP01SURFADDR( 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) GR3D_GLOBAL_SAMP01SURFADDR(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) GR3D_GLOBAL_SAMP01SURFADDR(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) GR3D_GLOBAL_SAMP01SURFADDR(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GR3D_GLOBAL_SAMP01SURFADDR(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) GR3D_GLOBAL_SAMP01SURFADDR(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) GR3D_GLOBAL_SAMP01SURFADDR(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) GR3D_GLOBAL_SAMP23SURFADDR( 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) GR3D_GLOBAL_SAMP23SURFADDR( 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) GR3D_GLOBAL_SAMP23SURFADDR( 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) GR3D_GLOBAL_SAMP23SURFADDR( 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) GR3D_GLOBAL_SAMP23SURFADDR( 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) GR3D_GLOBAL_SAMP23SURFADDR( 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) GR3D_GLOBAL_SAMP23SURFADDR( 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) GR3D_GLOBAL_SAMP23SURFADDR( 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) GR3D_GLOBAL_SAMP23SURFADDR( 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GR3D_GLOBAL_SAMP23SURFADDR( 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) GR3D_GLOBAL_SAMP23SURFADDR(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) GR3D_GLOBAL_SAMP23SURFADDR(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) GR3D_GLOBAL_SAMP23SURFADDR(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) GR3D_GLOBAL_SAMP23SURFADDR(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GR3D_GLOBAL_SAMP23SURFADDR(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) GR3D_GLOBAL_SAMP23SURFADDR(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int gr3d_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct host1x_syncpt **syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct gr3d *gr3d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!gr3d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gr3d->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!syncpts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) gr3d->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(gr3d->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(&pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return PTR_ERR(gr3d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (IS_ERR(gr3d->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(&pdev->dev, "cannot get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return PTR_ERR(gr3d->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (IS_ERR(gr3d->clk_secondary)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(&pdev->dev, "cannot get secondary clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return PTR_ERR(gr3d->clk_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "3d2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (IS_ERR(gr3d->rst_secondary)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(&pdev->dev, "cannot get secondary reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return PTR_ERR(gr3d->rst_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) gr3d->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_err(&pdev->dev, "failed to power up 3D unit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (gr3d->clk_secondary) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) gr3d->clk_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) gr3d->rst_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "failed to power up secondary 3D unit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) INIT_LIST_HEAD(&gr3d->client.base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) gr3d->client.base.ops = &gr3d_client_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) gr3d->client.base.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) gr3d->client.base.class = HOST1X_CLASS_GR3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) gr3d->client.base.syncpts = syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) gr3d->client.base.num_syncpts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) INIT_LIST_HEAD(&gr3d->client.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) gr3d->client.version = gr3d->soc->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) gr3d->client.ops = &gr3d_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err = host1x_client_register(&gr3d->client.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(&pdev->dev, "failed to register host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* initialize address register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) platform_set_drvdata(pdev, gr3d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int gr3d_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct gr3d *gr3d = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) err = host1x_client_unregister(&gr3d->client.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (gr3d->clk_secondary) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) reset_control_assert(gr3d->rst_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tegra_powergate_power_off(TEGRA_POWERGATE_3D1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) clk_disable_unprepare(gr3d->clk_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) reset_control_assert(gr3d->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tegra_powergate_power_off(TEGRA_POWERGATE_3D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk_disable_unprepare(gr3d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct platform_driver tegra_gr3d_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .name = "tegra-gr3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .of_match_table = tegra_gr3d_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .probe = gr3d_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .remove = gr3d_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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