Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012-2013, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "gem.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "gr2d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) struct gr2d_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct gr2d {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct tegra_drm_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct host1x_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	const struct gr2d_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static inline struct gr2d *to_gr2d(struct tegra_drm_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	return container_of(client, struct gr2d, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int gr2d_init(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct tegra_drm_client *drm = host1x_to_drm_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct drm_device *dev = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct gr2d *gr2d = to_gr2d(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	gr2d->channel = host1x_channel_request(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (!gr2d->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	client->syncpts[0] = host1x_syncpt_request(client, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (!client->syncpts[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		dev_err(client->dev, "failed to request syncpoint: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	err = host1x_client_iommu_attach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		dev_err(client->dev, "failed to attach to domain: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	err = tegra_drm_register_client(dev->dev_private, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		dev_err(client->dev, "failed to register client: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		goto detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) detach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	host1x_client_iommu_detach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	host1x_syncpt_free(client->syncpts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	host1x_channel_put(gr2d->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int gr2d_exit(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct tegra_drm_client *drm = host1x_to_drm_client(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct drm_device *dev = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct tegra_drm *tegra = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct gr2d *gr2d = to_gr2d(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	err = tegra_drm_unregister_client(tegra, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	host1x_client_iommu_detach(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	host1x_syncpt_free(client->syncpts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	host1x_channel_put(gr2d->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static const struct host1x_client_ops gr2d_client_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.init = gr2d_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.exit = gr2d_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int gr2d_open_channel(struct tegra_drm_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			     struct tegra_drm_context *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct gr2d *gr2d = to_gr2d(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	context->channel = host1x_channel_get(gr2d->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (!context->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void gr2d_close_channel(struct tegra_drm_context *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	host1x_channel_put(context->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct gr2d *gr2d = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	switch (class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case HOST1X_CLASS_HOST1X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		if (offset == 0x2b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case HOST1X_CLASS_GR2D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case HOST1X_CLASS_GR2D_SB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (offset >= GR2D_NUM_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (test_bit(offset, gr2d->addr_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int gr2d_is_valid_class(u32 class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return (class == HOST1X_CLASS_GR2D ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		class == HOST1X_CLASS_GR2D_SB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct tegra_drm_client_ops gr2d_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.open_channel = gr2d_open_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.close_channel = gr2d_close_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.is_addr_reg = gr2d_is_addr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.is_valid_class = gr2d_is_valid_class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.submit = tegra_drm_submit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct gr2d_soc tegra20_gr2d_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.version = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct gr2d_soc tegra30_gr2d_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.version = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct of_device_id gr2d_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ .compatible = "nvidia,tegra30-gr2d", .data = &tegra20_gr2d_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ .compatible = "nvidia,tegra20-gr2d", .data = &tegra30_gr2d_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MODULE_DEVICE_TABLE(of, gr2d_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const u32 gr2d_addr_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	GR2D_UA_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	GR2D_VA_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	GR2D_PAT_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	GR2D_DSTA_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	GR2D_DSTB_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	GR2D_DSTC_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	GR2D_SRCA_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	GR2D_SRCB_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	GR2D_PATBASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	GR2D_SRC_BASE_ADDR_SB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	GR2D_DSTA_BASE_ADDR_SB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	GR2D_DSTB_BASE_ADDR_SB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	GR2D_UA_BASE_ADDR_SB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	GR2D_VA_BASE_ADDR_SB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int gr2d_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct host1x_syncpt **syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct gr2d *gr2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (!gr2d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	gr2d->soc = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!syncpts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	gr2d->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (IS_ERR(gr2d->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		dev_err(dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return PTR_ERR(gr2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	err = clk_prepare_enable(gr2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(dev, "cannot turn on clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	INIT_LIST_HEAD(&gr2d->client.base.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	gr2d->client.base.ops = &gr2d_client_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	gr2d->client.base.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	gr2d->client.base.class = HOST1X_CLASS_GR2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	gr2d->client.base.syncpts = syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	gr2d->client.base.num_syncpts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	INIT_LIST_HEAD(&gr2d->client.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	gr2d->client.version = gr2d->soc->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	gr2d->client.ops = &gr2d_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	err = host1x_client_register(&gr2d->client.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		dev_err(dev, "failed to register host1x client: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		clk_disable_unprepare(gr2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* initialize address register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		set_bit(gr2d_addr_regs[i], gr2d->addr_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	platform_set_drvdata(pdev, gr2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int gr2d_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct gr2d *gr2d = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	err = host1x_client_unregister(&gr2d->client.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	clk_disable_unprepare(gr2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct platform_driver tegra_gr2d_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.name = "tegra-gr2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.of_match_table = gr2d_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.probe = gr2d_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.remove = gr2d_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };