Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012-2013 Avionic Design GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on the KMS/FB CMA helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Copyright (C) 2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <drm/drm_modeset_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "gem.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #ifdef CONFIG_DRM_FBDEV_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static inline struct tegra_fbdev *to_tegra_fbdev(struct drm_fb_helper *helper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	return container_of(helper, struct tegra_fbdev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 				    unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return to_tegra_bo(drm_gem_fb_get_obj(framebuffer, index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct tegra_bo *bo = tegra_fb_get_plane(framebuffer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	if (bo->flags & TEGRA_BO_BOTTOM_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			struct tegra_bo_tiling *tiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	uint64_t modifier = framebuffer->modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	switch (modifier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	case DRM_FORMAT_MOD_LINEAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		tiling->mode = TEGRA_BO_TILING_MODE_PITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		tiling->value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		tiling->mode = TEGRA_BO_TILING_MODE_TILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		tiling->value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		tiling->value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		tiling->value = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		tiling->value = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		tiling->value = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		tiling->value = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		tiling->value = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static const struct drm_framebuffer_funcs tegra_fb_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.destroy = drm_gem_fb_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.create_handle = drm_gem_fb_create_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					      const struct drm_mode_fb_cmd2 *mode_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					      struct tegra_bo **planes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 					      unsigned int num_planes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct drm_framebuffer *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	fb = kzalloc(sizeof(*fb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	for (i = 0; i < fb->format->num_planes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		fb->obj[i] = &planes[i]->gem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	err = drm_framebuffer_init(drm, fb, &tegra_fb_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		dev_err(drm->dev, "failed to initialize framebuffer: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		kfree(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 					struct drm_file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					const struct drm_mode_fb_cmd2 *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	const struct drm_format_info *info = drm_get_format_info(drm, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct tegra_bo *planes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct drm_gem_object *gem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct drm_framebuffer *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	for (i = 0; i < info->num_planes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		unsigned int width = cmd->width / (i ? info->hsub : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		unsigned int height = cmd->height / (i ? info->vsub : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		unsigned int size, bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		gem = drm_gem_object_lookup(file, cmd->handles[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (!gem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			goto unreference;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		bpp = info->cpp[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		size = (height - 1) * cmd->pitches[i] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		       width * bpp + cmd->offsets[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (gem->size < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			goto unreference;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		planes[i] = to_tegra_bo(gem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	fb = tegra_fb_alloc(drm, cmd, planes, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (IS_ERR(fb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		err = PTR_ERR(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		goto unreference;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unreference:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		drm_gem_object_put(&planes[i]->gem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef CONFIG_DRM_FBDEV_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int tegra_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct drm_fb_helper *helper = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct tegra_bo *bo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	bo = tegra_fb_get_plane(helper->fb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	err = drm_gem_mmap_obj(&bo->gem, bo->gem.size, vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return __tegra_gem_mmap(&bo->gem, vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct fb_ops tegra_fb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	DRM_FB_HELPER_DEFAULT_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.fb_fillrect = drm_fb_helper_sys_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.fb_copyarea = drm_fb_helper_sys_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.fb_imageblit = drm_fb_helper_sys_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.fb_mmap = tegra_fb_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int tegra_fbdev_probe(struct drm_fb_helper *helper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			     struct drm_fb_helper_surface_size *sizes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct tegra_fbdev *fbdev = to_tegra_fbdev(helper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct tegra_drm *tegra = helper->dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct drm_device *drm = helper->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct drm_mode_fb_cmd2 cmd = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned int bytes_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct drm_framebuffer *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct tegra_bo *bo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	cmd.width = sizes->surface_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	cmd.height = sizes->surface_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				  tegra->pitch_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 						     sizes->surface_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	size = cmd.pitches[0] * cmd.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	bo = tegra_bo_create(drm, size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (IS_ERR(bo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return PTR_ERR(bo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	info = drm_fb_helper_alloc_fbi(helper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (IS_ERR(info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		dev_err(drm->dev, "failed to allocate framebuffer info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		drm_gem_object_put(&bo->gem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return PTR_ERR(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	fbdev->fb = tegra_fb_alloc(drm, &cmd, &bo, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (IS_ERR(fbdev->fb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		err = PTR_ERR(fbdev->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		drm_gem_object_put(&bo->gem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return PTR_ERR(fbdev->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	fb = fbdev->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	helper->fb = fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	helper->fbdev = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	info->fbops = &tegra_fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	drm_fb_helper_fill_info(info, helper, sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	offset = info->var.xoffset * bytes_per_pixel +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		 info->var.yoffset * fb->pitches[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (bo->pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		bo->vaddr = vmap(bo->pages, bo->num_pages, VM_MAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				 pgprot_writecombine(PAGE_KERNEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		if (!bo->vaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			dev_err(drm->dev, "failed to vmap() framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			goto destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	drm->mode_config.fb_base = (resource_size_t)bo->iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	info->screen_base = (void __iomem *)bo->vaddr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	info->screen_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	info->fix.smem_start = (unsigned long)(bo->iova + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	info->fix.smem_len = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	drm_framebuffer_remove(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct drm_fb_helper_funcs tegra_fb_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.fb_probe = tegra_fbdev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct tegra_fbdev *tegra_fbdev_create(struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	struct tegra_fbdev *fbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (!fbdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		dev_err(drm->dev, "failed to allocate DRM fbdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	drm_fb_helper_prepare(drm, &fbdev->base, &tegra_fb_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return fbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void tegra_fbdev_free(struct tegra_fbdev *fbdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	kfree(fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int tegra_fbdev_init(struct tegra_fbdev *fbdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			    unsigned int preferred_bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			    unsigned int num_crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			    unsigned int max_connectors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct drm_device *drm = fbdev->base.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	err = drm_fb_helper_init(drm, &fbdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		dev_err(drm->dev, "failed to initialize DRM FB helper: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	err = drm_fb_helper_initial_config(&fbdev->base, preferred_bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		dev_err(drm->dev, "failed to set initial configuration: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		goto fini;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fini:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	drm_fb_helper_fini(&fbdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void tegra_fbdev_exit(struct tegra_fbdev *fbdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	drm_fb_helper_unregister_fbi(&fbdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (fbdev->fb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		struct tegra_bo *bo = tegra_fb_get_plane(fbdev->fb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		/* Undo the special mapping we made in fbdev probe. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		if (bo && bo->pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			vunmap(bo->vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			bo->vaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		drm_framebuffer_remove(fbdev->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	drm_fb_helper_fini(&fbdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	tegra_fbdev_free(fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int tegra_drm_fb_prepare(struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #ifdef CONFIG_DRM_FBDEV_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	tegra->fbdev = tegra_fbdev_create(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (IS_ERR(tegra->fbdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return PTR_ERR(tegra->fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void tegra_drm_fb_free(struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #ifdef CONFIG_DRM_FBDEV_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	tegra_fbdev_free(tegra->fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int tegra_drm_fb_init(struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #ifdef CONFIG_DRM_FBDEV_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	err = tegra_fbdev_init(tegra->fbdev, 32, drm->mode_config.num_crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			       drm->mode_config.num_connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) void tegra_drm_fb_exit(struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #ifdef CONFIG_DRM_FBDEV_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	struct tegra_drm *tegra = drm->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	tegra_fbdev_exit(tegra->fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }