^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _FALCON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _FALCON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FALCON_UCLASS_METHOD_OFFSET 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define FALCON_UCLASS_METHOD_DATA 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FALCON_IRQMSET 0x00001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FALCON_IRQMSET_WDTMR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FALCON_IRQMSET_HALT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FALCON_IRQMSET_EXTERR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FALCON_IRQMSET_SWGEN0 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FALCON_IRQMSET_SWGEN1 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FALCON_IRQMSET_EXT(v) (((v) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FALCON_IRQDEST 0x0000101c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FALCON_IRQDEST_HALT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FALCON_IRQDEST_EXTERR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FALCON_IRQDEST_SWGEN0 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FALCON_IRQDEST_SWGEN1 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FALCON_IRQDEST_EXT(v) (((v) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FALCON_ITFEN 0x00001048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FALCON_ITFEN_CTXEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FALCON_ITFEN_MTHDEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FALCON_IDLESTATE 0x0000104c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FALCON_CPUCTL 0x00001100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FALCON_CPUCTL_STARTCPU (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FALCON_BOOTVEC 0x00001104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FALCON_DMACTL 0x0000110c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FALCON_DMACTL_DMEM_SCRUBBING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FALCON_DMACTL_IMEM_SCRUBBING (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FALCON_DMATRFBASE 0x00001110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FALCON_DMATRFMOFFS 0x00001114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FALCON_DMATRFCMD 0x00001118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FALCON_DMATRFCMD_IDLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FALCON_DMATRFCMD_IMEM (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FALCON_DMATRFCMD_SIZE_256B (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FALCON_DMATRFFBOFFS 0x0000111c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct falcon_fw_bin_header_v1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 magic; /* 0x10de */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 version; /* version of bin format (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 size; /* entire image size including this header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 os_header_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 os_data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 os_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct falcon_fw_os_app_v1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct falcon_fw_os_header_v1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 code_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 code_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct falcon_firmware_section {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct falcon_firmware {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Firmware after it is read but not loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) const struct firmware *firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Raw firmware data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dma_addr_t iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Parsed firmware information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct falcon_firmware_section bin_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct falcon_firmware_section data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct falcon_firmware_section code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct falcon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Set by falcon client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct falcon_firmware firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int falcon_init(struct falcon *falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void falcon_exit(struct falcon *falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int falcon_read_firmware(struct falcon *falcon, const char *firmware_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int falcon_load_firmware(struct falcon *falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int falcon_boot(struct falcon *falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void falcon_execute_method(struct falcon *falcon, u32 method, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int falcon_wait_idle(struct falcon *falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif /* _FALCON_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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