Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "falcon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) enum falcon_memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	FALCON_MEMORY_IMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	FALCON_MEMORY_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static void falcon_writel(struct falcon *falcon, u32 value, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	writel(value, falcon->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) int falcon_wait_idle(struct falcon *falcon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return readl_poll_timeout(falcon->regs + FALCON_IDLESTATE, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				  (value == 0), 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static int falcon_dma_wait_idle(struct falcon *falcon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 				  (value & FALCON_DMATRFCMD_IDLE), 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static int falcon_copy_chunk(struct falcon *falcon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			     phys_addr_t base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			     unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			     enum falcon_memory target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 cmd = FALCON_DMATRFCMD_SIZE_256B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (target == FALCON_MEMORY_IMEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		cmd |= FALCON_DMATRFCMD_IMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	falcon_writel(falcon, cmd, FALCON_DMATRFCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return falcon_dma_wait_idle(falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static void falcon_copy_firmware_image(struct falcon *falcon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				       const struct firmware *firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u32 *virt = falcon->firmware.virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/* copy the whole thing taking into account endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	for (i = 0; i < firmware->size / sizeof(u32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		virt[i] = le32_to_cpu(((u32 *)firmware->data)[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int falcon_parse_firmware_image(struct falcon *falcon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct falcon_fw_os_header_v1 *os;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* endian problems would show up right here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (bin->magic != PCI_VENDOR_ID_NVIDIA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		dev_err(falcon->dev, "incorrect firmware magic\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* currently only version 1 is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (bin->version != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		dev_err(falcon->dev, "unsupported firmware version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* check that the firmware size is consistent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (bin->size > falcon->firmware.size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		dev_err(falcon->dev, "firmware image size inconsistency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	os = falcon->firmware.virt + bin->os_header_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	falcon->firmware.bin_data.size = bin->os_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	falcon->firmware.bin_data.offset = bin->os_data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	falcon->firmware.code.offset = os->code_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	falcon->firmware.code.size = os->code_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	falcon->firmware.data.offset = os->data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	falcon->firmware.data.size = os->data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int falcon_read_firmware(struct falcon *falcon, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* request_firmware prints error if it fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	err = request_firmware(&falcon->firmware.firmware, name, falcon->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	falcon->firmware.size = falcon->firmware.firmware->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int falcon_load_firmware(struct falcon *falcon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	const struct firmware *firmware = falcon->firmware.firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* copy firmware image into local area. this also ensures endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	falcon_copy_firmware_image(falcon, firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* parse the image data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	err = falcon_parse_firmware_image(falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		dev_err(falcon->dev, "failed to parse firmware image\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	release_firmware(firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	falcon->firmware.firmware = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int falcon_init(struct falcon *falcon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	falcon->firmware.virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void falcon_exit(struct falcon *falcon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (falcon->firmware.firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		release_firmware(falcon->firmware.firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int falcon_boot(struct falcon *falcon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!falcon->firmware.virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	err = readl_poll_timeout(falcon->regs + FALCON_DMACTL, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				 (value & (FALCON_DMACTL_IMEM_SCRUBBING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 					   FALCON_DMACTL_DMEM_SCRUBBING)) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				 10, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	falcon_writel(falcon, 0, FALCON_DMACTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* setup the address of the binary data so Falcon can access it later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	falcon_writel(falcon, (falcon->firmware.iova +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			       falcon->firmware.bin_data.offset) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		      FALCON_DMATRFBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* copy the data segment into Falcon internal memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	for (offset = 0; offset < falcon->firmware.data.size; offset += 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		falcon_copy_chunk(falcon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				  falcon->firmware.data.offset + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				  offset, FALCON_MEMORY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* copy the first code segment into Falcon internal memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	falcon_copy_chunk(falcon, falcon->firmware.code.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			  0, FALCON_MEMORY_IMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* setup falcon interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			      FALCON_IRQMSET_SWGEN1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			      FALCON_IRQMSET_SWGEN0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			      FALCON_IRQMSET_EXTERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			      FALCON_IRQMSET_HALT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			      FALCON_IRQMSET_WDTMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		      FALCON_IRQMSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	falcon_writel(falcon, FALCON_IRQDEST_EXT(0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			      FALCON_IRQDEST_SWGEN1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			      FALCON_IRQDEST_SWGEN0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			      FALCON_IRQDEST_EXTERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			      FALCON_IRQDEST_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		      FALCON_IRQDEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* enable interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	falcon_writel(falcon, FALCON_ITFEN_MTHDEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			      FALCON_ITFEN_CTXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		      FALCON_ITFEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* boot falcon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	falcon_writel(falcon, 0x00000000, FALCON_BOOTVEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	falcon_writel(falcon, FALCON_CPUCTL_STARTCPU, FALCON_CPUCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	err = falcon_wait_idle(falcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		dev_err(falcon->dev, "Falcon boot failed due to timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void falcon_execute_method(struct falcon *falcon, u32 method, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	falcon_writel(falcon, method >> 2, FALCON_UCLASS_METHOD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	falcon_writel(falcon, data, FALCON_UCLASS_METHOD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }