^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef DRM_TEGRA_DSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define DRM_TEGRA_DSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DSI_INCR_SYNCPT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DSI_INCR_SYNCPT_CONTROL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DSI_INCR_SYNCPT_ERROR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DSI_CTXSW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DSI_RD_DATA 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DSI_WR_DATA 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DSI_POWER_CONTROL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DSI_POWER_CONTROL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DSI_INT_ENABLE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DSI_INT_STATUS 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DSI_INT_MASK 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DSI_HOST_CONTROL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DSI_HOST_CONTROL_RAW (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DSI_HOST_CONTROL_HS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DSI_HOST_CONTROL_CS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DSI_HOST_CONTROL_ECC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DSI_CONTROL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DSI_CONTROL_DCS_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DSI_CONTROL_HOST_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DSI_SOL_DELAY 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DSI_MAX_THRESHOLD 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DSI_TRIGGER 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DSI_TRIGGER_HOST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DSI_TRIGGER_VIDEO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DSI_TX_CRC 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DSI_STATUS 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DSI_STATUS_IDLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DSI_STATUS_UNDERFLOW (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DSI_STATUS_OVERFLOW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DSI_INIT_SEQ_CONTROL 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DSI_INIT_SEQ_DATA_0 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DSI_INIT_SEQ_DATA_1 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DSI_INIT_SEQ_DATA_2 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DSI_INIT_SEQ_DATA_3 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DSI_INIT_SEQ_DATA_4 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DSI_INIT_SEQ_DATA_5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DSI_INIT_SEQ_DATA_6 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DSI_INIT_SEQ_DATA_7 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DSI_PKT_SEQ_0_LO 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DSI_PKT_SEQ_0_HI 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DSI_PKT_SEQ_1_LO 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DSI_PKT_SEQ_1_HI 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DSI_PKT_SEQ_2_LO 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DSI_PKT_SEQ_2_HI 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DSI_PKT_SEQ_3_LO 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DSI_PKT_SEQ_3_HI 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DSI_PKT_SEQ_4_LO 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DSI_PKT_SEQ_4_HI 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DSI_PKT_SEQ_5_LO 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DSI_PKT_SEQ_5_HI 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DSI_DCS_CMDS 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DSI_PKT_LEN_0_1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DSI_PKT_LEN_2_3 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DSI_PKT_LEN_4_5 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DSI_PKT_LEN_6_7 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DSI_PHY_TIMING_0 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DSI_PHY_TIMING_1 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DSI_PHY_TIMING_2 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DSI_BTA_TIMING 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DSI_TIMING_FIELD(value, period, hwinc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DSI_TIMEOUT_0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DSI_TIMEOUT_1 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DSI_TO_TALLY 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DSI_TALLY_TA(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DSI_PAD_CONTROL_0 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DSI_PAD_CONTROL_CD 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DSI_PAD_CD_STATUS 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DSI_VIDEO_MODE_CONTROL 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DSI_PAD_CONTROL_1 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DSI_PAD_CONTROL_2 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DSI_PAD_CONTROL_3 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DSI_PAD_CONTROL_4 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DSI_GANGED_MODE_CONTROL 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DSI_GANGED_MODE_START 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DSI_GANGED_MODE_SIZE 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DSI_RAW_DATA_BYTE_COUNT 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DSI_ULTRA_LOW_POWER_CONTROL 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DSI_INIT_SEQ_DATA_8 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DSI_INIT_SEQ_DATA_9 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DSI_INIT_SEQ_DATA_10 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DSI_INIT_SEQ_DATA_11 0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DSI_INIT_SEQ_DATA_12 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DSI_INIT_SEQ_DATA_13 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DSI_INIT_SEQ_DATA_14 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DSI_INIT_SEQ_DATA_15 0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * pixel format as used in the DSI_CONTROL_FORMAT field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum tegra_dsi_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) TEGRA_DSI_FORMAT_16P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) TEGRA_DSI_FORMAT_18NP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) TEGRA_DSI_FORMAT_18P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) TEGRA_DSI_FORMAT_24P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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