^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/host1x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "dc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "dsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "mipi-phy.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct tegra_dsi_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct drm_connector_state base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mipi_dphy_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int vrefresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long bclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum tegra_dsi_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline struct tegra_dsi_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) to_dsi_state(struct drm_connector_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return container_of(state, struct tegra_dsi_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct tegra_dsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct host1x_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct tegra_output output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct clk *clk_lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct drm_info_list *debugfs_files;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum mipi_dsi_pixel_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct tegra_mipi_device *mipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mipi_dsi_host host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct regulator *vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int video_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int host_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* for ganged-mode support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct tegra_dsi *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct tegra_dsi *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline struct tegra_dsi *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) host1x_client_to_dsi(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return container_of(client, struct tegra_dsi, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return container_of(host, struct tegra_dsi, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return container_of(output, struct tegra_dsi, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return to_dsi_state(dsi->output.connector.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 value = readl(dsi->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) trace_dsi_readl(dsi->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) trace_dsi_writel(dsi->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(value, dsi->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct debugfs_reg32 tegra_dsi_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEBUGFS_REG32(DSI_INCR_SYNCPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEBUGFS_REG32(DSI_CTXSW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEBUGFS_REG32(DSI_RD_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEBUGFS_REG32(DSI_WR_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEBUGFS_REG32(DSI_POWER_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEBUGFS_REG32(DSI_INT_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEBUGFS_REG32(DSI_INT_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEBUGFS_REG32(DSI_INT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEBUGFS_REG32(DSI_HOST_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEBUGFS_REG32(DSI_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEBUGFS_REG32(DSI_SOL_DELAY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEBUGFS_REG32(DSI_MAX_THRESHOLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEBUGFS_REG32(DSI_TRIGGER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEBUGFS_REG32(DSI_TX_CRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEBUGFS_REG32(DSI_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEBUGFS_REG32(DSI_DCS_CMDS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEBUGFS_REG32(DSI_PKT_LEN_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEBUGFS_REG32(DSI_PKT_LEN_2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEBUGFS_REG32(DSI_PKT_LEN_4_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEBUGFS_REG32(DSI_PKT_LEN_6_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEBUGFS_REG32(DSI_PHY_TIMING_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEBUGFS_REG32(DSI_PHY_TIMING_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEBUGFS_REG32(DSI_PHY_TIMING_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEBUGFS_REG32(DSI_BTA_TIMING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEBUGFS_REG32(DSI_TIMEOUT_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEBUGFS_REG32(DSI_TIMEOUT_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEBUGFS_REG32(DSI_TO_TALLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEBUGFS_REG32(DSI_PAD_CONTROL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEBUGFS_REG32(DSI_PAD_CD_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEBUGFS_REG32(DSI_PAD_CONTROL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEBUGFS_REG32(DSI_PAD_CONTROL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEBUGFS_REG32(DSI_PAD_CONTROL_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEBUGFS_REG32(DSI_PAD_CONTROL_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEBUGFS_REG32(DSI_GANGED_MODE_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int tegra_dsi_show_regs(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct drm_info_node *node = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct tegra_dsi *dsi = node->info_ent->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct drm_crtc *crtc = dsi->output.encoder.crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct drm_device *drm = node->minor->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) drm_modeset_lock_all(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!crtc || !crtc->state->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int offset = tegra_dsi_regs[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) offset, tegra_dsi_readl(dsi, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) drm_modeset_unlock_all(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct drm_info_list debugfs_files[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { "regs", tegra_dsi_show_regs, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int tegra_dsi_late_register(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct tegra_output *output = connector_to_output(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int i, count = ARRAY_SIZE(debugfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct drm_minor *minor = connector->dev->primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct dentry *root = connector->debugfs_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct tegra_dsi *dsi = to_dsi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!dsi->debugfs_files)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dsi->debugfs_files[i].data = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void tegra_dsi_early_unregister(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct tegra_output *output = connector_to_output(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int count = ARRAY_SIZE(debugfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct tegra_dsi *dsi = to_dsi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) drm_debugfs_remove_files(dsi->debugfs_files, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) connector->dev->primary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) kfree(dsi->debugfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dsi->debugfs_files = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PKT_LEN0(len) (((len) & 0x07) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PKT_LEN1(len) (((len) & 0x07) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PKT_LEN2(len) (((len) & 0x07) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PKT_LP (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define NUM_PKT_SEQ 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * non-burst mode with sync pulses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [ 1] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [ 3] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [ 5] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [ 9] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * non-burst mode with sync events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [ 1] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [ 3] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [ 5] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [ 9] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [ 0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [ 1] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [ 2] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [ 3] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [ 4] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [ 5] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [ 7] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [ 8] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [ 9] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [11] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const struct mipi_dphy_timing *timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DSI_TIMING_FIELD(timing->hsprepare, period, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DSI_TIMING_FIELD(timing->lpx, period, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DSI_TIMING_FIELD(timing->tago, period, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tegra_dsi_set_phy_timing(dsi->slave, period, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int *mulp, unsigned int *divp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case MIPI_DSI_FMT_RGB666_PACKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case MIPI_DSI_FMT_RGB888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *mulp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *divp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case MIPI_DSI_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *mulp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *divp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case MIPI_DSI_FMT_RGB666:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *mulp = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *divp = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) enum tegra_dsi_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case MIPI_DSI_FMT_RGB888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *fmt = TEGRA_DSI_FORMAT_24P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case MIPI_DSI_FMT_RGB666:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *fmt = TEGRA_DSI_FORMAT_18NP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case MIPI_DSI_FMT_RGB666_PACKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *fmt = TEGRA_DSI_FORMAT_18P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case MIPI_DSI_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *fmt = TEGRA_DSI_FORMAT_16P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) value = DSI_GANGED_MODE_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void tegra_dsi_enable(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) value |= DSI_POWER_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tegra_dsi_enable(dsi->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (dsi->master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return dsi->master->lanes + dsi->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return dsi->lanes + dsi->slave->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return dsi->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int hact, hsw, hbp, hfp, i, mul, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct tegra_dsi_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const u32 *pkt_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* XXX: pass in state into this function? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (dsi->master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) state = tegra_dsi_get_state(dsi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) state = tegra_dsi_get_state(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mul = state->mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) div = state->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) pkt_seq = pkt_seq_video_non_burst_sync_pulses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pkt_seq = pkt_seq_video_non_burst_sync_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DRM_DEBUG_KMS("Command mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pkt_seq = pkt_seq_command_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) value = DSI_CONTROL_CHANNEL(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DSI_CONTROL_FORMAT(state->format) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DSI_CONTROL_LANES(dsi->lanes - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DSI_CONTROL_SOURCE(pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tegra_dsi_writel(dsi, value, DSI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) value = DSI_HOST_CONTROL_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) value = tegra_dsi_readl(dsi, DSI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) value |= DSI_CONTROL_HS_CLK_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) value &= ~DSI_CONTROL_TX_TRIG(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* enable DCS commands for command mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (dsi->flags & MIPI_DSI_MODE_VIDEO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) value &= ~DSI_CONTROL_DCS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) value |= DSI_CONTROL_DCS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) value |= DSI_CONTROL_VIDEO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) value &= ~DSI_CONTROL_HOST_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tegra_dsi_writel(dsi, value, DSI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) for (i = 0; i < NUM_PKT_SEQ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* horizontal active pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hact = mode->hdisplay * mul / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* horizontal sync width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* horizontal back porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hbp = (mode->htotal - mode->hsync_end) * mul / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hbp += hsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* horizontal front porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* subtract packet overhead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hsw -= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) hbp -= 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hfp -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* set SOL delay (for non-burst mode only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* TODO: implement ganged mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u16 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (dsi->master || dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * For ganged mode, assume symmetric left-right mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bytes = 1 + (mode->hdisplay / 2) * mul / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* 1 byte (DCS command) + pixel data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bytes = 1 + mode->hdisplay * mul / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) value = MIPI_DCS_WRITE_MEMORY_START << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MIPI_DCS_WRITE_MEMORY_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* set SOL delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (dsi->master || dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned long delay, bclk, bclk_ganged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int lanes = state->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* SOL to valid, valid to FIFO and FIFO write delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) delay = 4 + 4 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) delay = DIV_ROUND_UP(delay * mul, div * lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* FIFO read delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) delay = delay + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) value = bclk - bclk_ganged + delay + 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* TODO: revisit for non-ganged mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) value = 8 * mul / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tegra_dsi_configure(dsi->slave, pipe, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * TODO: Support modes other than symmetrical left-right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * split.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mode->hdisplay / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) timeout = jiffies + msecs_to_jiffies(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) value = tegra_dsi_readl(dsi, DSI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (value & DSI_STATUS_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) value = tegra_dsi_readl(dsi, DSI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) value &= ~DSI_CONTROL_VIDEO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) tegra_dsi_writel(dsi, value, DSI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tegra_dsi_video_disable(dsi->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * XXX Is this still needed? The module reset is deasserted right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * before this function is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* start calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) tegra_dsi_pad_enable(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) DSI_PAD_OUT_CLK(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) err = tegra_mipi_start_calibration(dsi->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return tegra_mipi_finish_calibration(dsi->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned int vrefresh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* one frame high-speed transmission timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) timeout = (bclk / vrefresh) / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* 2 ms peripheral timeout for panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) timeout = 2 * bclk / 512 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void tegra_dsi_disable(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) tegra_dsi_ganged_disable(dsi->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tegra_dsi_ganged_disable(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) value &= ~DSI_POWER_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) tegra_dsi_disable(dsi->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) value &= ~DSI_POWER_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) usleep_range(300, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) value |= DSI_POWER_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) usleep_range(300, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) value = tegra_dsi_readl(dsi, DSI_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) tegra_dsi_soft_reset(dsi->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void tegra_dsi_connector_reset(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (connector->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __drm_atomic_helper_connector_destroy_state(connector->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) kfree(connector->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) __drm_atomic_helper_connector_reset(connector, &state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static struct drm_connector_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct tegra_dsi_state *state = to_dsi_state(connector->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct tegra_dsi_state *copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!copy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) __drm_atomic_helper_connector_duplicate_state(connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ©->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ©->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .reset = tegra_dsi_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .detect = tegra_output_connector_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .destroy = tegra_output_connector_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .late_register = tegra_dsi_late_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .early_unregister = tegra_dsi_early_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) tegra_dsi_connector_mode_valid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .get_modes = tegra_output_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .mode_valid = tegra_dsi_connector_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tegra_dsi_unprepare(dsi->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) err = tegra_mipi_disable(dsi->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) err = host1x_client_suspend(&dsi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_err(dsi->dev, "failed to suspend: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct tegra_dsi *dsi = to_dsi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (output->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) drm_panel_disable(output->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) tegra_dsi_video_disable(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * The following accesses registers of the display controller, so make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * sure it's only executed when the output is attached to one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (dc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) value &= ~DSI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) tegra_dc_commit(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) err = tegra_dsi_wait_idle(dsi, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) tegra_dsi_soft_reset(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (output->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) drm_panel_unprepare(output->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) tegra_dsi_disable(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) tegra_dsi_unprepare(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int tegra_dsi_prepare(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) err = host1x_client_resume(&dsi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(dsi->dev, "failed to resume: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) err = tegra_mipi_enable(dsi->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) err = tegra_dsi_pad_calibrate(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (dsi->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) tegra_dsi_prepare(dsi->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct tegra_dsi *dsi = to_dsi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct tegra_dsi_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) err = tegra_dsi_prepare(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(dsi->dev, "failed to prepare: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) state = tegra_dsi_get_state(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * The D-PHY timing fields are expressed in byte-clock cycles, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * multiply the period by 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (output->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) drm_panel_prepare(output->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) tegra_dsi_configure(dsi, dc->pipe, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* enable display controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) value |= DSI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) tegra_dc_commit(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* enable DSI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) tegra_dsi_enable(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (output->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) drm_panel_enable(output->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct tegra_output *output = encoder_to_output(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct tegra_dsi_state *state = to_dsi_state(conn_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct tegra_dsi *dsi = to_dsi(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned int scdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) unsigned long plld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) state->pclk = crtc_state->mode.clock * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) state->lanes = tegra_dsi_get_lanes(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) err = tegra_dsi_get_format(dsi->format, &state->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* compute byte clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) state->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) state->vrefresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * Compute bit clock and round up to the next MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) err = mipi_dphy_timing_get_default(&state->timing, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) err = mipi_dphy_timing_validate(&state->timing, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * We divide the frequency by two here, but we make up for that by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * setting the shift clock divider (further below) to half of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * correct value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) plld /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * Derive pixel clock from bit clock using the shift clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * Note that this is only half of what we would expect, but we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * that to make up for the fact that we divided the bit clock by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * factor of two above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * It's not clear exactly why this is necessary, but the display is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * not working properly otherwise. Perhaps the PLLs cannot generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * frequencies sufficiently high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) plld, scdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .disable = tegra_dsi_encoder_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .enable = tegra_dsi_encoder_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .atomic_check = tegra_dsi_encoder_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static int tegra_dsi_init(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct drm_device *drm = dev_get_drvdata(client->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct tegra_dsi *dsi = host1x_client_to_dsi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Gangsters must not register their own outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!dsi->master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dsi->output.dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) drm_connector_init(drm, &dsi->output.connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) &tegra_dsi_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) drm_connector_helper_add(&dsi->output.connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) &tegra_dsi_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) drm_simple_encoder_init(drm, &dsi->output.encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) DRM_MODE_ENCODER_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) drm_encoder_helper_add(&dsi->output.encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) &tegra_dsi_encoder_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) drm_connector_attach_encoder(&dsi->output.connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) &dsi->output.encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) drm_connector_register(&dsi->output.connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) err = tegra_output_init(drm, &dsi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev_err(dsi->dev, "failed to initialize output: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dsi->output.encoder.possible_crtcs = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int tegra_dsi_exit(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct tegra_dsi *dsi = host1x_client_to_dsi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) tegra_output_exit(&dsi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int tegra_dsi_runtime_suspend(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct tegra_dsi *dsi = host1x_client_to_dsi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct device *dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (dsi->rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) err = reset_control_assert(dsi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev_err(dev, "failed to assert reset: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) clk_disable_unprepare(dsi->clk_lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) clk_disable_unprepare(dsi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) regulator_disable(dsi->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int tegra_dsi_runtime_resume(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct tegra_dsi *dsi = host1x_client_to_dsi(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct device *dev = client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) err = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dev_err(dev, "failed to get runtime PM: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) err = regulator_enable(dsi->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_err(dev, "failed to enable VDD supply: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto put_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) err = clk_prepare_enable(dsi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev_err(dev, "cannot enable DSI clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) goto disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) err = clk_prepare_enable(dsi->clk_lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_err(dev, "cannot enable low-power clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (dsi->rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) err = reset_control_deassert(dsi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev_err(dev, "cannot assert reset: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) goto disable_clk_lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) disable_clk_lp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) clk_disable_unprepare(dsi->clk_lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) clk_disable_unprepare(dsi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) disable_vdd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) regulator_disable(dsi->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) put_rpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static const struct host1x_client_ops dsi_client_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .init = tegra_dsi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .exit = tegra_dsi_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .suspend = tegra_dsi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .resume = tegra_dsi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) parent = clk_get_parent(dsi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) err = clk_set_parent(parent, dsi->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static const char * const error_report[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) "SoT Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) "SoT Sync Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "EoT Sync Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "Escape Mode Entry Command Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "Low-Power Transmit Sync Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "Peripheral Timeout Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) "False Control Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) "Contention Detected",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) "ECC Error, single-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) "ECC Error, multi-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) "Checksum Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "DSI Data Type Not Recognized",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "DSI VC ID Invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "Invalid Transmission Length",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) "DSI Protocol Violation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) const struct mipi_dsi_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u8 *rx = msg->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) unsigned int i, j, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) size_t size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u16 errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* read and parse packet header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) value = tegra_dsi_readl(dsi, DSI_RD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) switch (value & 0x3f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) errors = (value >> 8) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) for (i = 0; i < ARRAY_SIZE(error_report); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (errors & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_dbg(dsi->dev, " %2u: %s\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) error_report[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) rx[0] = (value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) rx[0] = (value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) rx[1] = (value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_err(dsi->dev, "unhandled response type: %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) value & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) size = min(size, msg->rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (msg->rx_buf && size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) for (i = 0, j = 0; i < count - 1; i++, j += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u8 *rx = msg->rx_buf + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) value = tegra_dsi_readl(dsi, DSI_RD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) rx[j + k] = (value >> (k << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) timeout = jiffies + msecs_to_jiffies(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if ((value & DSI_TRIGGER_HOST) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) timeout = jiffies + msecs_to_jiffies(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u8 count = value & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) DRM_DEBUG_KMS("peripheral returned no data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) const void *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) const u8 *buf = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) size_t i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) for (j = 0; j < size; j += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) for (i = 0; i < 4 && j + i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) value |= buf[j + i] << (i << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) tegra_dsi_writel(dsi, value, DSI_WR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) const struct mipi_dsi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct tegra_dsi *dsi = host_to_tegra(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct mipi_dsi_packet packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) const u8 *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ssize_t err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) err = mipi_dsi_create_packet(&packet, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) header = packet.header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* maximum FIFO depth is 1920 words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (packet.size > dsi->video_fifo_depth * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* reset underflow/overflow flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) value = tegra_dsi_readl(dsi, DSI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) value = DSI_HOST_CONTROL_FIFO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) value |= DSI_POWER_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) value |= DSI_HOST_CONTROL_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * The host FIFO has a maximum of 64 words, so larger transmissions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * need to use the video FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (packet.size > dsi->host_fifo_depth * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) value |= DSI_HOST_CONTROL_FIFO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * For reads and messages with explicitly requested ACK, generate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * BTA sequence after the transmission of the packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) (msg->rx_buf && msg->rx_len > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) value |= DSI_HOST_CONTROL_PKT_BTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) tegra_dsi_writel(dsi, value, DSI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* write packet header, ECC is generated by hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) value = header[2] << 16 | header[1] << 8 | header[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) tegra_dsi_writel(dsi, value, DSI_WR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* write payload (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (packet.payload_length > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) packet.payload_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) err = tegra_dsi_transmit(dsi, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) (msg->rx_buf && msg->rx_len > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) err = tegra_dsi_wait_for_response(dsi, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) count = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) value = tegra_dsi_readl(dsi, DSI_RD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) case 0x84:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dev_dbg(dsi->dev, "ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) case 0x87:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dev_dbg(dsi->dev, "ESCAPE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev_err(dsi->dev, "unknown status: %08x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) err = tegra_dsi_read_response(dsi, msg, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dev_err(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) "failed to parse response: %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * For read commands, return the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * bytes returned by the peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) count = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * For write commands, we have transmitted the 4-byte header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * plus the variable-length payload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) count = 4 + packet.payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* make sure both DSI controllers share the same PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) parent = clk_get_parent(dsi->slave->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) err = clk_set_parent(parent, dsi->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct mipi_dsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) struct tegra_dsi *dsi = host_to_tegra(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) dsi->flags = device->mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) dsi->format = device->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) dsi->lanes = device->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dev_name(&device->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) err = tegra_dsi_ganged_setup(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * Slaves don't have a panel associated with them, so they provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * merely the second channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!dsi->master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct tegra_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) output->panel = of_drm_find_panel(device->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (IS_ERR(output->panel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) output->panel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (output->panel && output->connector.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) drm_helper_hpd_irq_event(output->connector.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct mipi_dsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct tegra_dsi *dsi = host_to_tegra(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct tegra_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (output->panel && &device->dev == output->panel->dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) output->panel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (output->connector.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) drm_helper_hpd_irq_event(output->connector.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .attach = tegra_dsi_host_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .detach = tegra_dsi_host_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .transfer = tegra_dsi_host_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct platform_device *gangster = of_find_device_by_node(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dsi->slave = platform_get_drvdata(gangster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!dsi->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) put_device(&gangster->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dsi->slave->master = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int tegra_dsi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct tegra_dsi *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (!dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) dsi->output.dev = dsi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dsi->video_fifo_depth = 1920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dsi->host_fifo_depth = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) err = tegra_dsi_ganged_probe(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) err = tegra_output_probe(&dsi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * Assume these values by default. When a DSI peripheral driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * attaches to the DSI host, the parameters will be taken from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * the attached device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) dsi->flags = MIPI_DSI_MODE_VIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (!pdev->dev.pm_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (IS_ERR(dsi->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return PTR_ERR(dsi->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dsi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (IS_ERR(dsi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_err(&pdev->dev, "cannot get DSI clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return PTR_ERR(dsi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (IS_ERR(dsi->clk_lp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_err(&pdev->dev, "cannot get low-power clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return PTR_ERR(dsi->clk_lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (IS_ERR(dsi->clk_parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dev_err(&pdev->dev, "cannot get parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return PTR_ERR(dsi->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (IS_ERR(dsi->vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) dev_err(&pdev->dev, "cannot get VDD supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return PTR_ERR(dsi->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) err = tegra_dsi_setup_clocks(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) dev_err(&pdev->dev, "cannot setup clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (IS_ERR(dsi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return PTR_ERR(dsi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (IS_ERR(dsi->mipi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return PTR_ERR(dsi->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) dsi->host.ops = &tegra_dsi_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dsi->host.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) err = mipi_dsi_host_register(&dsi->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) goto mipi_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) platform_set_drvdata(pdev, dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) INIT_LIST_HEAD(&dsi->client.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dsi->client.ops = &dsi_client_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dsi->client.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) err = host1x_client_register(&dsi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dev_err(&pdev->dev, "failed to register host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) mipi_dsi_host_unregister(&dsi->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) mipi_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) tegra_mipi_free(dsi->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static int tegra_dsi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct tegra_dsi *dsi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) err = host1x_client_unregister(&dsi->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) tegra_output_remove(&dsi->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) mipi_dsi_host_unregister(&dsi->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) tegra_mipi_free(dsi->mipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static const struct of_device_id tegra_dsi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) { .compatible = "nvidia,tegra210-dsi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) { .compatible = "nvidia,tegra132-dsi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) { .compatible = "nvidia,tegra124-dsi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) { .compatible = "nvidia,tegra114-dsi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) struct platform_driver tegra_dsi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .name = "tegra-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .of_match_table = tegra_dsi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .probe = tegra_dsi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .remove = tegra_dsi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags