Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2013 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef DRM_TEGRA_DPAUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define DRM_TEGRA_DPAUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define DPAUX_CTXSW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DPAUX_INTR_EN_AUX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DPAUX_INTR_AUX 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DPAUX_INTR_AUX_DONE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DPAUX_INTR_IRQ_EVENT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DPAUX_INTR_UNPLUG_EVENT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DPAUX_INTR_PLUG_EVENT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DPAUX_DP_AUXDATA_WRITE(x) (0x09 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DPAUX_DP_AUXDATA_READ(x) (0x19 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DPAUX_DP_AUXADDR 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DPAUX_DP_AUXCTL 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DPAUX_DP_AUXCTL_TRANSACTREQ (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DPAUX_DP_AUXCTL_CMD_AUX_RD (9 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DPAUX_DP_AUXCTL_CMD_AUX_WR (8 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DPAUX_DP_AUXCTL_CMD_MOT_RQ (6 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DPAUX_DP_AUXCTL_CMD_MOT_RD (5 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DPAUX_DP_AUXCTL_CMD_MOT_WR (4 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DPAUX_DP_AUXCTL_CMD_I2C_RQ (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPAUX_DP_AUXCTL_CMD_I2C_RD (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DPAUX_DP_AUXCTL_CMD_I2C_WR (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DPAUX_DP_AUXCTL_CMDLEN(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DPAUX_DP_AUXSTAT 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DPAUX_DP_AUXSTAT_HPD_STATUS (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK (0xf0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DPAUX_DP_AUXSTAT_RX_ERROR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DPAUX_DP_AUXSTAT_REPLY_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DPAUX_DP_AUX_SINKSTAT_LO 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DPAUX_DP_AUX_SINKSTAT_HI 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DPAUX_HPD_CONFIG 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DPAUX_HPD_CONFIG_PLUG_MIN_TIME(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DPAUX_HPD_IRQ_CONFIG 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DPAUX_DP_AUX_CONFIG 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DPAUX_HYBRID_PADCTL 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DPAUX_HYBRID_PADCTL_AUX_CMH(x) (((x) & 0x3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DPAUX_HYBRID_PADCTL_AUX_DRVZ(x) (((x) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DPAUX_HYBRID_PADCTL_AUX_DRVI(x) (((x) & 0x3f) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DPAUX_HYBRID_PADCTL_MODE_I2C (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DPAUX_HYBRID_PADCTL_MODE_AUX (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DPAUX_HYBRID_SPARE 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DPAUX_HYBRID_SPARE_PAD_POWER_DOWN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DPAUX_SCRATCH_REG0 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DPAUX_SCRATCH_REG1 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DPAUX_SCRATCH_REG2 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif