^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: MIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-2019 NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Rob Clark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DRM_TEGRA_DP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRM_TEGRA_DP_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct drm_display_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct drm_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct drm_dp_aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct drm_dp_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * struct drm_dp_link_caps - DP link capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct drm_dp_link_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @enhanced_framing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * enhanced framing capability (mandatory as of DP 1.2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bool enhanced_framing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * tps3_supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * training pattern sequence 3 supported for equalization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) bool tps3_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @fast_training:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * AUX CH handshake not required for link training
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool fast_training;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @channel_coding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * ANSI 8B/10B channel coding capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bool channel_coding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @alternate_scrambler_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * eDP alternate scrambler reset capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool alternate_scrambler_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct drm_dp_link_caps *src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * struct drm_dp_link_ops - DP link operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct drm_dp_link_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @apply_training:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int (*apply_training)(struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @configure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int (*configure)(struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * struct drm_dp_link_train_set - link training settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @voltage_swing: per-lane voltage swing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @pre_emphasis: per-lane pre-emphasis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @post_cursor: per-lane post-cursor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct drm_dp_link_train_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int voltage_swing[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int pre_emphasis[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int post_cursor[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * struct drm_dp_link_train - link training state information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @request: currently requested settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @adjust: adjustments requested by sink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @pattern: currently requested training pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @clock_recovered: flag to track if clock recovery has completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @channel_equalized: flag to track if channel equalization has completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct drm_dp_link_train {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct drm_dp_link_train_set request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct drm_dp_link_train_set adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bool clock_recovered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bool channel_equalized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * struct drm_dp_link - DP link capabilities and configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @revision: DP specification revision supported on the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @max_rate: maximum clock rate supported on the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @max_lanes: maximum number of lanes supported on the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @caps: capabilities supported on the link (see &drm_dp_link_caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @aux_rd_interval: AUX read interval to use for training (in microseconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @rate: currently configured link rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @lanes: currently configured number of lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @rates: additional supported link rates in kHz (eDP 1.4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @num_rates: number of additional supported link rates (eDP 1.4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct drm_dp_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned char revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int max_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct drm_dp_link_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @cr: clock recovery read interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @ce: channel equalization read interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } aux_rd_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned char edp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long rates[DP_MAX_SUPPORTED_RATES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int num_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @ops: DP link operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct drm_dp_link_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @aux: DP AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct drm_dp_aux *aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @train: DP link training state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct drm_dp_link_train train;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void drm_dp_link_update_rates(struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int drm_dp_link_choose(struct drm_dp_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const struct drm_display_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void drm_dp_link_train_init(struct drm_dp_link_train *train);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int drm_dp_link_train(struct drm_dp_link *link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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