^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: MIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-2019 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Rob Clark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <drm/drm_dp_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "dp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const u8 drm_dp_edp_revisions[] = { 0x11, 0x12, 0x13, 0x14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) caps->enhanced_framing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) caps->tps3_supported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) caps->fast_training = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) caps->channel_coding = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) caps->alternate_scrambler_reset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) const struct drm_dp_link_caps *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dest->enhanced_framing = src->enhanced_framing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) dest->tps3_supported = src->tps3_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) dest->fast_training = src->fast_training;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) dest->channel_coding = src->channel_coding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) dest->alternate_scrambler_reset = src->alternate_scrambler_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void drm_dp_link_reset(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) link->revision = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) link->max_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) link->max_lanes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) drm_dp_link_caps_reset(&link->caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) link->aux_rd_interval.cr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) link->aux_rd_interval.ce = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) link->edp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) link->rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) link->lanes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) link->rates[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) link->num_rates = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * drm_dp_link_add_rate() - add a rate to the list of supported rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @link: the link to add the rate to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @rate: the rate to add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Add a link rate to the list of supported link rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 0 on success or one of the following negative error codes on failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * - ENOSPC if the maximum number of supported rates has been reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - EEXISTS if the link already supports this rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * See also:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * drm_dp_link_remove_rate()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int i, pivot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (link->num_rates == DP_MAX_SUPPORTED_RATES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) for (pivot = 0; pivot < link->num_rates; pivot++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (rate <= link->rates[pivot])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (pivot != link->num_rates && rate == link->rates[pivot])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) for (i = link->num_rates; i > pivot; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) link->rates[i] = link->rates[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) link->rates[pivot] = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) link->num_rates++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * drm_dp_link_remove_rate() - remove a rate from the list of supported rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @link: the link from which to remove the rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @rate: the rate to remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Removes a link rate from the list of supported link rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 0 on success or one of the following negative error codes on failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * - EINVAL if the specified rate is not among the supported rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * See also:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * drm_dp_link_add_rate()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (i = 0; i < link->num_rates; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (rate == link->rates[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (i == link->num_rates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) link->num_rates--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) while (i < link->num_rates) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) link->rates[i] = link->rates[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * drm_dp_link_update_rates() - normalize the supported link rates array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @link: the link for which to normalize the supported link rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Users should call this function after they've manually modified the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * of supported link rates. This function removes any stale entries, compacts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * the array and updates the supported link rate count. Note that calling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * drm_dp_link_remove_rate() function already does this janitorial work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * See also:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * drm_dp_link_add_rate(), drm_dp_link_remove_rate()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void drm_dp_link_update_rates(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) for (i = 0; i < link->num_rates; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (link->rates[i] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) link->rates[count++] = link->rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = count; i < link->num_rates; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) link->rates[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) link->num_rates = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * drm_dp_link_probe() - probe a DisplayPort link for capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @aux: DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @link: pointer to structure in which to return link capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * The structure filled in by this function can usually be passed directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * configure the link based on the link's capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Returns 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 dpcd[DP_RECEIVER_CAP_SIZE], value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int rd_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) drm_dp_link_reset(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) link->revision = dpcd[DP_DPCD_REV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) link->max_rate = drm_dp_max_link_rate(dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) link->max_lanes = drm_dp_max_lane_count(dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) link->caps.tps3_supported = drm_dp_tps3_supported(dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) link->caps.fast_training = drm_dp_fast_training_cap(dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) link->caps.alternate_scrambler_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (value >= ARRAY_SIZE(drm_dp_edp_revisions))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DRM_ERROR("unsupported eDP version: %02x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) link->edp = drm_dp_edp_revisions[value];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * The DPCD stores the AUX read interval in units of 4 ms. There are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * two special cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 1) if the TRAINING_AUX_RD_INTERVAL field is 0, the clock recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * and channel equalization should use 100 us or 400 us AUX read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * intervals, respectively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * 2) for DP v1.4 and above, clock recovery should always use 100 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * AUX read intervals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DP_TRAINING_AUX_RD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (rd_interval > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DRM_DEBUG_KMS("AUX interval %u out of range (max. 4)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rd_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rd_interval = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rd_interval *= 4 * USEC_PER_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (rd_interval == 0 || link->revision >= DP_DPCD_REV_14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) link->aux_rd_interval.cr = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (rd_interval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) link->aux_rd_interval.ce = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) link->rate = link->max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) link->lanes = link->max_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Parse SUPPORTED_LINK_RATES from eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (link->edp >= 0x14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 supported_rates[DP_MAX_SUPPORTED_RATES * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u16 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) err = drm_dp_dpcd_read(aux, DP_SUPPORTED_LINK_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) supported_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sizeof(supported_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rate = supported_rates[i * 2 + 1] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) supported_rates[i * 2 + 0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) drm_dp_link_add_rate(link, rate * 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * drm_dp_link_power_up() - power up a DisplayPort link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @aux: DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @link: pointer to a structure containing the link configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Returns 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* DP_SET_POWER register is only available on DPCD v1.1 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (link->revision < 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) value &= ~DP_SET_POWER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) value |= DP_SET_POWER_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * According to the DP 1.1 specification, a "Sink Device must exit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Control Field" (register 0x600).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * drm_dp_link_power_down() - power down a DisplayPort link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @aux: DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @link: pointer to a structure containing the link configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Returns 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* DP_SET_POWER register is only available on DPCD v1.1 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (link->revision < 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) value &= ~DP_SET_POWER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) value |= DP_SET_POWER_D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * drm_dp_link_configure() - configure a DisplayPort link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @aux: DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @link: pointer to a structure containing the link configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Returns 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 values[2], value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (link->ops && link->ops->configure) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err = link->ops->configure(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DRM_ERROR("failed to configure DP link: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) values[0] = drm_dp_link_rate_to_bw_code(link->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) values[1] = link->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (link->caps.enhanced_framing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (link->caps.channel_coding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) value = DP_SET_ANSI_8B10B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (link->caps.alternate_scrambler_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * drm_dp_link_choose() - choose the lowest possible configuration for a mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @link: DRM DP link object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * @mode: DRM display mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @info: DRM display information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * According to the eDP specification, a source should select a configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * with the lowest number of lanes and the lowest possible link rate that can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * match the bitrate requirements of a video mode. However it must ensure not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * to exceed the capabilities of the sink.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Returns: 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int drm_dp_link_choose(struct drm_dp_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) const struct drm_display_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* available link symbol clock rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const unsigned int rates[3] = { 162000, 270000, 540000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* available number of lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const unsigned int lanes[3] = { 1, 2, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned long requirement, capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int rate = link->max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* bandwidth requirement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) requirement = mode->clock * info->bpc * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (j = 0; j < ARRAY_SIZE(rates) && rates[j] <= rate; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Capacity for this combination of lanes and rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * factoring in the ANSI 8B/10B encoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Link rates in the DRM DP helpers are really link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * symbol frequencies, so a tenth of the actual rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * of the link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) capacity = lanes[i] * (rates[j] * 10) * 8 / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (capacity >= requirement) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DRM_DEBUG_KMS("using %u lanes at %u kHz (%lu/%lu kbps)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) lanes[i], rates[j], requirement,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) capacity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) link->lanes = lanes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) link->rate = rates[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * DOC: Link training
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * These functions contain common logic and helpers to implement DisplayPort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * link training.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * drm_dp_link_train_init() - initialize DisplayPort link training state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @train: DisplayPort link training state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void drm_dp_link_train_init(struct drm_dp_link_train *train)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct drm_dp_link_train_set *request = &train->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct drm_dp_link_train_set *adjust = &train->adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) request->voltage_swing[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) adjust->voltage_swing[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) request->pre_emphasis[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) adjust->pre_emphasis[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) request->post_cursor[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) adjust->post_cursor[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) train->pattern = DP_TRAINING_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) train->clock_recovered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) train->channel_equalized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static bool drm_dp_link_train_valid(const struct drm_dp_link_train *train)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return train->clock_recovered && train->channel_equalized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int drm_dp_link_apply_training(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct drm_dp_link_train_set *request = &link->train.request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int lanes = link->lanes, *vs, *pe, *pc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct drm_dp_aux *aux = link->aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 values[4], pattern = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) err = link->ops->apply_training(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DRM_ERROR("failed to apply link training: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) vs = request->voltage_swing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pe = request->pre_emphasis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pc = request->post_cursor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* write currently selected voltage-swing and pre-emphasis levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) for (i = 0; i < lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) values[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL(vs[i]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DP_TRAIN_PRE_EMPHASIS_LEVEL(pe[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DRM_ERROR("failed to set training parameters: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* write currently selected post-cursor level (if supported) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (link->revision >= 0x12 && link->rate == 540000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) values[0] = values[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (i = 0; i < lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) values[i / 2] |= DP_LANE_POST_CURSOR(i, pc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_1_SET2, values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DIV_ROUND_UP(lanes, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DRM_ERROR("failed to set post-cursor: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* write link pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (link->train.pattern != DP_TRAINING_PATTERN_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pattern |= DP_LINK_SCRAMBLING_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pattern |= link->train.pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DRM_ERROR("failed to set training pattern: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void drm_dp_link_train_wait(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) switch (link->train.pattern) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case DP_TRAINING_PATTERN_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) min = link->aux_rd_interval.cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case DP_TRAINING_PATTERN_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case DP_TRAINING_PATTERN_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) min = link->aux_rd_interval.ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (min > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) usleep_range(min, 2 * min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void drm_dp_link_get_adjustments(struct drm_dp_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u8 status[DP_LINK_STATUS_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct drm_dp_link_train_set *adjust = &link->train.adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (i = 0; i < link->lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) adjust->voltage_swing[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) drm_dp_get_adjust_request_voltage(status, i) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) DP_TRAIN_VOLTAGE_SWING_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) adjust->pre_emphasis[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) drm_dp_get_adjust_request_pre_emphasis(status, i) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) DP_TRAIN_PRE_EMPHASIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) adjust->post_cursor[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) drm_dp_get_adjust_request_post_cursor(status, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void drm_dp_link_train_adjust(struct drm_dp_link_train *train)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct drm_dp_link_train_set *request = &train->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct drm_dp_link_train_set *adjust = &train->adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (request->voltage_swing[i] != adjust->voltage_swing[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) request->voltage_swing[i] = adjust->voltage_swing[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (request->pre_emphasis[i] != adjust->pre_emphasis[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) request->pre_emphasis[i] = adjust->pre_emphasis[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (request->post_cursor[i] != adjust->post_cursor[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) request->post_cursor[i] = adjust->post_cursor[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int drm_dp_link_recover_clock(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 status[DP_LINK_STATUS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) err = drm_dp_link_apply_training(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) drm_dp_link_train_wait(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) err = drm_dp_dpcd_read_link_status(link->aux, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DRM_ERROR("failed to read link status: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!drm_dp_clock_recovery_ok(status, link->lanes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) drm_dp_link_get_adjustments(link, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) link->train.clock_recovered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int drm_dp_link_clock_recovery(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int repeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* start clock recovery using training pattern 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) link->train.pattern = DP_TRAINING_PATTERN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) for (repeat = 1; repeat < 5; repeat++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) err = drm_dp_link_recover_clock(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) DRM_ERROR("failed to recover clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (link->train.clock_recovered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) drm_dp_link_train_adjust(&link->train);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int drm_dp_link_equalize_channel(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct drm_dp_aux *aux = link->aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u8 status[DP_LINK_STATUS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) err = drm_dp_link_apply_training(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) drm_dp_link_train_wait(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) err = drm_dp_dpcd_read_link_status(aux, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) DRM_ERROR("failed to read link status: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) DRM_ERROR("clock recovery lost while equalizing channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) link->train.clock_recovered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!drm_dp_channel_eq_ok(status, link->lanes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) drm_dp_link_get_adjustments(link, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) link->train.channel_equalized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int drm_dp_link_channel_equalization(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) unsigned int repeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* start channel equalization using pattern 2 or 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (link->caps.tps3_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) link->train.pattern = DP_TRAINING_PATTERN_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) link->train.pattern = DP_TRAINING_PATTERN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) for (repeat = 1; repeat < 5; repeat++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) err = drm_dp_link_equalize_channel(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) DRM_ERROR("failed to equalize channel: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (link->train.channel_equalized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) drm_dp_link_train_adjust(&link->train);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int drm_dp_link_downgrade(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) switch (link->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case 162000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case 270000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) link->rate = 162000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case 540000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) link->rate = 270000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static void drm_dp_link_train_disable(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) link->train.pattern = DP_TRAINING_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) err = drm_dp_link_apply_training(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) DRM_ERROR("failed to disable link training: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int drm_dp_link_train_full(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) DRM_DEBUG_KMS("full-training link: %u lane%s at %u MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) link->lanes, (link->lanes > 1) ? "s" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) link->rate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) err = drm_dp_link_configure(link->aux, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) DRM_ERROR("failed to configure DP link: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) err = drm_dp_link_clock_recovery(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) DRM_ERROR("clock recovery failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (!link->train.clock_recovered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) DRM_ERROR("clock recovery failed, downgrading link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) err = drm_dp_link_downgrade(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) DRM_DEBUG_KMS("clock recovery succeeded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) err = drm_dp_link_channel_equalization(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DRM_ERROR("channel equalization failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!link->train.channel_equalized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) DRM_ERROR("channel equalization failed, downgrading link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) err = drm_dp_link_downgrade(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DRM_DEBUG_KMS("channel equalization succeeded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) drm_dp_link_train_disable(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int drm_dp_link_train_fast(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u8 status[DP_LINK_STATUS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DRM_DEBUG_KMS("fast-training link: %u lane%s at %u MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) link->lanes, (link->lanes > 1) ? "s" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) link->rate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) err = drm_dp_link_configure(link->aux, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DRM_ERROR("failed to configure DP link: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* transmit training pattern 1 for 500 microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) link->train.pattern = DP_TRAINING_PATTERN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) err = drm_dp_link_apply_training(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* transmit training pattern 2 or 3 for 500 microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (link->caps.tps3_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) link->train.pattern = DP_TRAINING_PATTERN_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) link->train.pattern = DP_TRAINING_PATTERN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) err = drm_dp_link_apply_training(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) err = drm_dp_dpcd_read_link_status(link->aux, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DRM_ERROR("failed to read link status: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) DRM_ERROR("clock recovery failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!drm_dp_channel_eq_ok(status, link->lanes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) DRM_ERROR("channel equalization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) drm_dp_link_train_disable(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * drm_dp_link_train() - perform DisplayPort link training
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * @link: a DP link object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Uses the context stored in the DP link object to perform link training. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * is expected that drivers will call drm_dp_link_probe() to obtain the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * capabilities before performing link training.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * If the sink supports fast link training (no AUX CH handshake) and valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * training settings are available, this function will try to perform fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * link training and fall back to full link training on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * Returns: 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int drm_dp_link_train(struct drm_dp_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) drm_dp_link_train_init(&link->train);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (link->caps.fast_training) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (drm_dp_link_train_valid(&link->train)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) err = drm_dp_link_train_fast(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) DRM_ERROR("fast link training failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) DRM_DEBUG_KMS("training parameters not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) DRM_DEBUG_KMS("fast link training not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) err = drm_dp_link_train_full(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) DRM_ERROR("full link training failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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