^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 Avionic Design GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef TEGRA_DC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define TEGRA_DC_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/host1x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct tegra_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct tegra_dc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct drm_crtc_state base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 planes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return container_of(state, struct tegra_dc_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct tegra_dc_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long underflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct tegra_windowgroup_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const unsigned int *windows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int num_windows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct tegra_dc_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool supports_background_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool supports_interlacing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool supports_cursor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool supports_block_linear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bool has_legacy_blending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int pitch_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool has_powergate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bool coupled_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bool has_nvdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct tegra_windowgroup_soc *wgrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int num_wgrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const u32 *primary_formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int num_primary_formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const u32 *overlay_formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int num_overlay_formats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const u64 *modifiers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool has_win_a_without_filters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool has_win_c_without_vert_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct tegra_dc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct host1x_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct host1x_syncpt *syncpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct drm_crtc base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int powergate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct tegra_output *rgb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct tegra_dc_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct drm_info_list *debugfs_files;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct tegra_dc_soc_info *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline struct tegra_dc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) host1x_client_to_dc(struct host1x_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return container_of(client, struct tegra_dc, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) trace_dc_writel(dc->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel(value, dc->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 value = readl(dc->regs + (offset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) trace_dc_readl(dc->dev, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct tegra_dc_window {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int stride[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long base[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int zpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bool reflect_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bool reflect_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct tegra_bo_tiling tiling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* from dc.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void tegra_dc_commit(struct tegra_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int tegra_dc_state_setup_clock(struct tegra_dc *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct clk *clk, unsigned long pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* from rgb.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int tegra_dc_rgb_probe(struct tegra_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int tegra_dc_rgb_remove(struct tegra_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int tegra_dc_rgb_exit(struct tegra_dc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SYNCPT_CNTRL_NO_STALL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DC_CMD_WIN_C_INCR_SYNCPT 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DC_CMD_CONT_SYNCPT_VSYNC 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SYNCPT_VSYNC_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DC_CMD_DISPLAY_COMMAND 0x032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DISP_CTRL_MODE_STOP (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DISP_CTRL_MODE_MASK (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DC_CMD_SIGNAL_RAISE 0x033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DC_CMD_DISPLAY_POWER_CONTROL 0x036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PW0_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PW1_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PW2_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PW3_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PW4_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PM0_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PM1_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DC_CMD_INT_STATUS 0x037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DC_CMD_INT_MASK 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DC_CMD_INT_ENABLE 0x039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DC_CMD_INT_TYPE 0x03a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DC_CMD_INT_POLARITY 0x03b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CTXSW_INT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FRAME_END_INT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define VBLANK_INT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define V_PULSE3_INT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define V_PULSE2_INT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define REGION_CRC_INT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define REG_TMOUT_INT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define WIN_A_UF_INT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define WIN_B_UF_INT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define WIN_C_UF_INT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MSF_INT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define WIN_A_OF_INT (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define WIN_B_OF_INT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define WIN_C_OF_INT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HEAD_UF_INT (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SD3_BUCKET_WALK_DONE_INT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DSC_OBUF_UF_INT (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DSC_RBUF_UF_INT (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DSC_BBUF_UF_INT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DSC_TO_UF_INT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DC_CMD_SIGNAL_RAISE1 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DC_CMD_SIGNAL_RAISE2 0x03d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DC_CMD_SIGNAL_RAISE3 0x03e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DC_CMD_STATE_ACCESS 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define READ_MUX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define WRITE_MUX (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DC_CMD_STATE_CONTROL 0x041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GENERAL_ACT_REQ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define WIN_A_ACT_REQ (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define WIN_B_ACT_REQ (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define WIN_C_ACT_REQ (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CURSOR_ACT_REQ (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GENERAL_UPDATE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define WIN_A_UPDATE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define WIN_B_UPDATE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define WIN_C_UPDATE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CURSOR_UPDATE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define COMMON_ACTREQ (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define COMMON_UPDATE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define NC_HOST_TRIG (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define WINDOW_A_SELECT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define WINDOW_B_SELECT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define WINDOW_C_SELECT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DC_CMD_REG_ACT_CONTROL 0x043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DC_COM_CRC_CONTROL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DC_COM_CRC_CONTROL_WAIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DC_COM_CRC_CHECKSUM 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define LVS_OUTPUT_POLARITY_LOW (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define LHS_OUTPUT_POLARITY_LOW (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DC_COM_PIN_MISC_CONTROL 0x31b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DC_COM_PIN_PM0_CONTROL 0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DC_COM_PIN_PM1_CONTROL 0x31e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DC_COM_SPI_CONTROL 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DC_COM_SPI_START_BYTE 0x321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DC_COM_HSPI_WRITE_DATA_AB 0x322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DC_COM_HSPI_WRITE_DATA_CD 0x323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DC_COM_HSPI_CS_DC 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DC_COM_SCRATCH_REGISTER_A 0x325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DC_COM_SCRATCH_REGISTER_B 0x326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DC_COM_GPIO_CTRL 0x327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DC_COM_CRC_CHECKSUM_LATCHED 0x329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DC_COM_RG_UNDERFLOW 0x365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define UNDERFLOW_MODE_RED (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define UNDERFLOW_REPORT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define H_PULSE0_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define H_PULSE1_ENABLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define H_PULSE2_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DC_DISP_DISP_WIN_OPTIONS 0x402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HDMI_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DSI_ENABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SOR1_TIMING_CYA (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CURSOR_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DC_DISP_DISP_TIMING_OPTIONS 0x405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define VSYNC_H_POSITION(x) ((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DC_DISP_REF_TO_SYNC 0x406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DC_DISP_SYNC_WIDTH 0x407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DC_DISP_BACK_PORCH 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DC_DISP_ACTIVE 0x409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DC_DISP_FRONT_PORCH 0x40a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DC_DISP_H_PULSE0_CONTROL 0x40b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DC_DISP_H_PULSE0_POSITION_A 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DC_DISP_H_PULSE0_POSITION_B 0x40d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DC_DISP_H_PULSE0_POSITION_C 0x40e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DC_DISP_H_PULSE0_POSITION_D 0x40f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DC_DISP_H_PULSE1_CONTROL 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DC_DISP_H_PULSE1_POSITION_A 0x411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DC_DISP_H_PULSE1_POSITION_B 0x412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DC_DISP_H_PULSE1_POSITION_C 0x413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DC_DISP_H_PULSE1_POSITION_D 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DC_DISP_H_PULSE2_CONTROL 0x415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DC_DISP_H_PULSE2_POSITION_A 0x416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DC_DISP_H_PULSE2_POSITION_B 0x417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DC_DISP_H_PULSE2_POSITION_C 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DC_DISP_H_PULSE2_POSITION_D 0x419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DC_DISP_V_PULSE0_CONTROL 0x41a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DC_DISP_V_PULSE0_POSITION_A 0x41b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DC_DISP_V_PULSE0_POSITION_B 0x41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DC_DISP_V_PULSE0_POSITION_C 0x41d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DC_DISP_V_PULSE1_CONTROL 0x41e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DC_DISP_V_PULSE1_POSITION_A 0x41f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DC_DISP_V_PULSE1_POSITION_B 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DC_DISP_V_PULSE1_POSITION_C 0x421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DC_DISP_V_PULSE2_CONTROL 0x422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DC_DISP_V_PULSE2_POSITION_A 0x423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DC_DISP_V_PULSE3_CONTROL 0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DC_DISP_V_PULSE3_POSITION_A 0x425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DC_DISP_M0_CONTROL 0x426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DC_DISP_M1_CONTROL 0x427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DC_DISP_DI_CONTROL 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DC_DISP_PP_CONTROL 0x429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DC_DISP_PP_SELECT_A 0x42a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DC_DISP_PP_SELECT_B 0x42b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DC_DISP_PP_SELECT_C 0x42c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DC_DISP_PP_SELECT_D 0x42d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PULSE_MODE_NORMAL (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PULSE_MODE_ONE_CLOCK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PULSE_POLARITY_HIGH (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PULSE_POLARITY_LOW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PULSE_QUAL_ALWAYS (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PULSE_QUAL_VACTIVE (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PULSE_QUAL_VACTIVE1 (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PULSE_LAST_START_A (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define PULSE_LAST_END_A (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PULSE_LAST_START_B (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PULSE_LAST_END_B (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PULSE_LAST_START_C (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PULSE_LAST_END_C (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PULSE_LAST_START_D (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PULSE_LAST_END_D (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PULSE_START(x) (((x) & 0xfff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PULSE_END(x) (((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DC_DISP_DISP_CLOCK_CONTROL 0x42e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DISP_DATA_FORMAT_DF1P1C (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DISP_DATA_FORMAT_DF2S (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DISP_DATA_FORMAT_DF3S (5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DISP_DATA_FORMAT_DFSPI (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DISP_ALIGNMENT_MSB (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DISP_ALIGNMENT_LSB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DISP_ORDER_RED_BLUE (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define DISP_ORDER_BLUE_RED (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DC_DISP_DISP_COLOR_CONTROL 0x430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define BASE_COLOR_SIZE666 ( 0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define BASE_COLOR_SIZE111 ( 1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define BASE_COLOR_SIZE222 ( 2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define BASE_COLOR_SIZE333 ( 3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define BASE_COLOR_SIZE444 ( 4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define BASE_COLOR_SIZE555 ( 5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define BASE_COLOR_SIZE565 ( 6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define BASE_COLOR_SIZE332 ( 7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define BASE_COLOR_SIZE888 ( 8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define BASE_COLOR_SIZE101010 (10 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define BASE_COLOR_SIZE121212 (12 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DITHER_CONTROL_MASK (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DITHER_CONTROL_DISABLE (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DITHER_CONTROL_ORDERED (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define DITHER_CONTROL_ERRDIFF (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BASE_COLOR_SIZE_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define BASE_COLOR_SIZE_666 ( 0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BASE_COLOR_SIZE_111 ( 1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define BASE_COLOR_SIZE_222 ( 2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define BASE_COLOR_SIZE_333 ( 3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define BASE_COLOR_SIZE_444 ( 4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BASE_COLOR_SIZE_555 ( 5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BASE_COLOR_SIZE_565 ( 6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define BASE_COLOR_SIZE_332 ( 7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define BASE_COLOR_SIZE_888 ( 8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define BASE_COLOR_SIZE_101010 ( 10 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define BASE_COLOR_SIZE_121212 ( 12 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SC1_H_QUALIFIER_NONE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SC0_H_QUALIFIER_NONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define DC_DISP_DATA_ENABLE_OPTIONS 0x432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DE_SELECT_ACTIVE_BLANK (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define DE_SELECT_ACTIVE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define DE_SELECT_ACTIVE_IS (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define DE_CONTROL_ONECLK (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define DE_CONTROL_NORMAL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define DE_CONTROL_EARLY_EXT (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define DE_CONTROL_EARLY (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DE_CONTROL_ACTIVE_BLANK (4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DC_DISP_LCD_SPI_OPTIONS 0x434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DC_DISP_BORDER_COLOR 0x435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define DC_DISP_COLOR_KEY0_LOWER 0x436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define DC_DISP_COLOR_KEY0_UPPER 0x437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DC_DISP_COLOR_KEY1_LOWER 0x438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define DC_DISP_COLOR_KEY1_UPPER 0x439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define DC_DISP_CURSOR_FOREGROUND 0x43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DC_DISP_CURSOR_BACKGROUND 0x43d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define DC_DISP_CURSOR_START_ADDR 0x43e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CURSOR_CLIP_DISPLAY (0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CURSOR_CLIP_WIN_A (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CURSOR_CLIP_WIN_B (2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CURSOR_CLIP_WIN_C (3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CURSOR_SIZE_32x32 (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CURSOR_SIZE_64x64 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CURSOR_SIZE_128x128 (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CURSOR_SIZE_256x256 (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define DC_DISP_CURSOR_START_ADDR_NS 0x43f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define DC_DISP_CURSOR_POSITION 0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define DC_DISP_CURSOR_POSITION_NS 0x441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DC_DISP_INIT_SEQ_CONTROL 0x442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DC_DISP_DAC_CRT_CTRL 0x4c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DC_DISP_DISP_MISC_CONTROL 0x4c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DC_DISP_SD_CONTROL 0x4c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DC_DISP_SD_CSC_COEFF 0x4c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DC_DISP_SD_LUT(x) (0x4c4 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DC_DISP_SD_FLICKER_CONTROL 0x4cd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DC_DISP_DC_PIXEL_COUNT 0x4ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DC_DISP_SD_BL_PARAMETERS 0x4d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DC_DISP_SD_BL_CONTROL 0x4dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DC_DISP_SD_HW_K_VALUES 0x4dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DC_DISP_SD_MAN_K_VALUES 0x4de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DC_DISP_INTERLACE_CONTROL 0x4e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define INTERLACE_STATUS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define INTERLACE_START (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define INTERLACE_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define CURSOR_MODE_LEGACY (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define CURSOR_MODE_NORMAL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define CURSOR_DST_BLEND_ZERO (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define CURSOR_DST_BLEND_K1 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define CURSOR_DST_BLEND_MASK (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define CURSOR_SRC_BLEND_K1 (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define CURSOR_SRC_BLEND_MASK (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define CURSOR_ALPHA 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DC_WIN_CORE_ACT_CONTROL 0x50e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define VCOUNTER (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define HCOUNTER (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define LATENCY_CTL_MODE_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define WATERMARK_MASK 0x1fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PIPE_METER_INT(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SLOTS(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MODE_TWO_LINES (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MODE_FOUR_LINES (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define THREAD_NUM_MASK (0x1f << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define THREAD_NUM(x) (((x) & 0x1f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define THREAD_GROUP_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define DC_WIN_H_FILTER_P(p) (0x601 + (p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define DC_WIN_V_FILTER_P(p) (0x619 + (p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define DC_WIN_CSC_YOF 0x611
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DC_WIN_CSC_KYRGB 0x612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define DC_WIN_CSC_KUR 0x613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define DC_WIN_CSC_KVR 0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define DC_WIN_CSC_KUG 0x615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define DC_WIN_CSC_KVG 0x616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define DC_WIN_CSC_KUB 0x617
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define DC_WIN_CSC_KVB 0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define DC_WIN_WIN_OPTIONS 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define H_DIRECTION (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define V_DIRECTION (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define COLOR_EXPAND (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define H_FILTER (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define V_FILTER (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define CSC_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define WIN_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define DC_WIN_BYTE_SWAP 0x701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define BYTE_SWAP_NOSWAP (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define BYTE_SWAP_SWAP2 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define BYTE_SWAP_SWAP4 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define BYTE_SWAP_SWAP4HW (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define DC_WIN_BUFFER_CONTROL 0x702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define BUFFER_CONTROL_HOST (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define BUFFER_CONTROL_VI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define BUFFER_CONTROL_EPP (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define BUFFER_CONTROL_MPEGE (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define BUFFER_CONTROL_SB2D (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DC_WIN_COLOR_DEPTH 0x703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define WIN_COLOR_DEPTH_P1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define WIN_COLOR_DEPTH_P2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define WIN_COLOR_DEPTH_P4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define WIN_COLOR_DEPTH_P8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define WIN_COLOR_DEPTH_B4G4R4A4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define WIN_COLOR_DEPTH_B5G5R5A1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define WIN_COLOR_DEPTH_B5G6R5 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define WIN_COLOR_DEPTH_A1B5G5R5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define WIN_COLOR_DEPTH_B8G8R8A8 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define WIN_COLOR_DEPTH_R8G8B8A8 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define WIN_COLOR_DEPTH_YCbCr422 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define WIN_COLOR_DEPTH_YUV422 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define WIN_COLOR_DEPTH_YCbCr420P 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define WIN_COLOR_DEPTH_YUV420P 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define WIN_COLOR_DEPTH_YCbCr422P 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define WIN_COLOR_DEPTH_YUV422P 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define WIN_COLOR_DEPTH_YCbCr422R 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define WIN_COLOR_DEPTH_YUV422R 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define WIN_COLOR_DEPTH_YCbCr422RA 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define WIN_COLOR_DEPTH_YUV422RA 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define WIN_COLOR_DEPTH_R4G4B4A4 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define WIN_COLOR_DEPTH_R5G5B5A 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define WIN_COLOR_DEPTH_AR5G5B5 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define WIN_COLOR_DEPTH_B5G5R5X1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define WIN_COLOR_DEPTH_X1B5G5R5 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define WIN_COLOR_DEPTH_R5G5B5X1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define WIN_COLOR_DEPTH_X1R5G5B5 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define WIN_COLOR_DEPTH_R5G6B5 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define WIN_COLOR_DEPTH_A8R8G8B8 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define WIN_COLOR_DEPTH_A8B8G8R8 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define WIN_COLOR_DEPTH_B8G8R8X8 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define WIN_COLOR_DEPTH_R8G8B8X8 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define WIN_COLOR_DEPTH_X8B8G8R8 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define WIN_COLOR_DEPTH_X8R8G8B8 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define DC_WIN_POSITION 0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define DC_WIN_SIZE 0x705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define DC_WIN_PRESCALED_SIZE 0x706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define DC_WIN_H_INITIAL_DDA 0x707
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define DC_WIN_V_INITIAL_DDA 0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define DC_WIN_DDA_INC 0x709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define H_DDA_INC(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define V_DDA_INC(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define DC_WIN_LINE_STRIDE 0x70a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define DC_WIN_BUF_STRIDE 0x70b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define DC_WIN_UV_BUF_STRIDE 0x70c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define DC_WIN_BUFFER_ADDR_MODE 0x70d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define DC_WIN_DV_CONTROL 0x70e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DC_WIN_BLEND_NOKEY 0x70f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define DC_WIN_BLEND_1WIN 0x710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define BLEND_CONTROL_FIX (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define BLEND_CONTROL_ALPHA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define BLEND_COLOR_KEY_NONE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define BLEND_COLOR_KEY_0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define BLEND_COLOR_KEY_1 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define BLEND_COLOR_KEY_BOTH (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define DC_WIN_BLEND_2WIN_X 0x711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define BLEND_CONTROL_DEPENDENT (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define DC_WIN_BLEND_2WIN_Y 0x712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define DC_WIN_BLEND_3WIN_XY 0x713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define DC_WIN_HP_FETCH_CONTROL 0x714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DC_WINBUF_START_ADDR 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define DC_WINBUF_START_ADDR_NS 0x801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define DC_WINBUF_START_ADDR_U 0x802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define DC_WINBUF_START_ADDR_U_NS 0x803
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define DC_WINBUF_START_ADDR_V 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define DC_WINBUF_START_ADDR_V_NS 0x805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define DC_WINBUF_ADDR_H_OFFSET 0x806
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define DC_WINBUF_ADDR_V_OFFSET 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define DC_WINBUF_UFLOW_STATUS 0x80a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define DC_WINBUF_SURFACE_KIND 0x80b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define DC_WINBUF_START_ADDR_HI 0x80d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define DC_WINBUF_CDE_CONTROL 0x82f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define ENABLE_SURFACE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define DC_WINBUF_AD_UFLOW_STATUS 0xbca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define DC_WINBUF_BD_UFLOW_STATUS 0xdca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define DC_WINBUF_CD_UFLOW_STATUS 0xfca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Tegra186 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define PROTOCOL_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define OWNER_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define OWNER(x) (((x) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define DC_WIN_CROPPED_SIZE 0x706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define DC_WIN_PLANAR_STORAGE 0x709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define PITCH(x) (((x) >> 6) & 0x1fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define DC_WIN_SET_PARAMS 0x70d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define CLAMP_BEFORE_BLEND (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define DEGAMMA_NONE (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define DEGAMMA_SRGB (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define DEGAMMA_YUV8_10 (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define DEGAMMA_YUV12 (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define INPUT_RANGE_BYPASS (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define INPUT_RANGE_LIMITED (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define INPUT_RANGE_FULL (2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define COLOR_SPACE_RGB (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define COLOR_SPACE_YUV_601 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define COLOR_SPACE_YUV_709 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define COLOR_SPACE_YUV_2020 (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define HORIZONTAL_TAPS_2 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define HORIZONTAL_TAPS_5 (4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define VERTICAL_TAPS_2 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define VERTICAL_TAPS_5 (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define INPUT_SCALER_USE422 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define INPUT_SCALER_VBYPASS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define INPUT_SCALER_HBYPASS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define DC_WIN_BLEND_LAYER_CONTROL 0x716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define COLOR_KEY_NONE (0 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define COLOR_KEY_SRC (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define COLOR_KEY_DST (2 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define BLEND_BYPASS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define K2(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define K1(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define DC_WIN_BLEND_MATCH_SELECT 0x717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define BLEND_FACTOR_DST_COLOR_ONE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define BLEND_FACTOR_DST_COLOR_K1 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define BLEND_FACTOR_DST_COLOR_K2 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define DC_WIN_BLEND_NOMATCH_SELECT 0x718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define SWAP_UV (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define DC_WIN_WINDOW_SET_CONTROL 0x730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define CONTROL_CSC_ENABLE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define DC_WINBUF_CROPPED_POINT 0x806
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define OFFSET_Y(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define OFFSET_X(x) (((x) & 0xffff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #endif /* TEGRA_DC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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