Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) STMicroelectronics SA 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Authors: Philippe Cornu <philippe.cornu@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *          Yannick Fertre <yannick.fertre@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *          Fabien Dessenne <fabien.dessenne@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *          Mickael Reulier <mickael.reulier@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _LTDC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _LTDC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct ltdc_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	u32 hw_version;		/* hardware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	u32 nb_layers;		/* number of supported layers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	u32 reg_ofs;		/* register offset for applicable regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	u32 bus_width;		/* bus width (32 or 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	const u32 *pix_fmt_hw;	/* supported pixel formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	int pad_max_freq_hz;	/* max frequency supported by pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	int nb_irq;		/* number of hardware interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LTDC_MAX_LAYER	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct fps_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	unsigned int counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	ktime_t last_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct ltdc_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	struct clk *pixel_clk;	/* lcd pixel clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct mutex err_lock;	/* protecting error_status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	struct ltdc_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u32 error_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct fps_info plane_fpsi[LTDC_MAX_LAYER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct drm_atomic_state *suspend_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int ltdc_load(struct drm_device *ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void ltdc_unload(struct drm_device *ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void ltdc_suspend(struct drm_device *ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int ltdc_resume(struct drm_device *ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif