Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) 1. stiH display hardware IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - The High Quality Video Display Processor (HQVDP) gets video frames from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   video decoder and does high quality video processing, including scaling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   has several inputs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - The graphics planes are internally processed by the Generic Display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     Pipeline (GDP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - The video plug (VID) connects to the HQVDP output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - The cursor handles ... a cursor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - The TV OUT pre-formats (convert, clip, round) the compositor output data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - The HDMI / DVO / HD Analog / SD analog IP builds the video signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - DVO (Digital Video Output) handles a 24bits parallel signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - The HD analog signal is typically driven by a YCbCr cable, supporting up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     1080i mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - The SD analog signal is typically used for legacy TV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Note that some stiH drivers support only a subset of thee HW IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)                   .-------------.   .-----------.   .-----------.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) GPU >-------------+GDP     Main |   |           +---+    HDMI   +--> HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) GPU >-------------+GDP     mixer+---+           |   :===========:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) GPU >-------------+Cursor       |   |           +---+    DVO    +--> 24b//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)         -------   |  COMPOSITOR |   |  TV OUT   |   :===========:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)        |       |  |             |   |           +---+ HD analog +--> YCbCr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Vid >--+ HQVDP +--+VID     Aux  +---+           |   :===========:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) dec    |       |  |        mixer|   |           +---+ SD analog +--> CVBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)        '-------'  '-------------'   '-----------'   '-----------'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)                    .-----------.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)                    |       main+--> Vsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)                    | VTG       |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)                    |        aux+--> Vsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)                    '-----------'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 2. DRM / HW mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) These IP are mapped to the DRM objects as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - The CRTCs are mapped to the Compositor Main and Aux Mixers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - The Framebuffers and planes are mapped to the Compositor GDP (non video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   buffers) and to HQVDP+VID (video buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - The Cursor is mapped to the Compositor Cursor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - The Encoders are mapped to the TVOut
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FB & planes         Cursor      CRTC     Encoders    Bridges/Connectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)    |                   |          |         |                       |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)    |                   |          |         |                       |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)    |              .-------------. | .-----------.   .-----------.   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)    +------------> |GDP |   Main | | |       +-> |   |    HDMI   | <-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)    +------------> |GDP v   mixer|<+ |       |   |   :===========:   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)    |              |Cursor       | | |       +-> |   |    DVO    | <-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)    |    -------   |  COMPOSITOR | | |TV OUT |   |   :===========:   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)    |   |       |  |             | | |       +-> |   | HD analog | <-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)    +-> | HQVDP |  |VID     Aux  |<+ |       |   |   :===========:   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)        |       |  |        mixer|   |       +-> |   | SD analog | <-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)        '-------'  '-------------'   '-----------'   '-----------'