^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef ROCKCHIP_MIPI_CSI_TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define ROCKCHIP_MIPI_CSI_TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DRIVER_NAME "rockchip-mipi-csi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CSITX_CONFIG_DONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define m_CONFIG_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define m_CONFIG_DONE_IMD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define m_CONFIG_DONE_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define v_CONFIG_DONE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define v_CONFIG_DONE_IMD(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define v_CONFIG_DONE_MODE(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum CONFIG_DONE_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) FRAME_END_RX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) FRAME_END_TX_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CSITX_ENABLE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define m_CSITX_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define m_CPHY_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define m_DPHY_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define m_LANE_NUM GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define m_IDI_48BIT_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define v_CSITX_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define v_CPHY_EN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define v_DPHY_EN(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define v_LANE_NUM(x) (((x) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define v_IDI_48BIT_EN(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CSITX_VERSION 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CSITX_SYS_CTRL0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define m_SOFT_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define v_SOFT_RESET(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CSITX_SYS_CTRL1 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define m_BYPASS_SELECT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define v_BYPASS_SELECT(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CSITX_SYS_CTRL2 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define m_VSYNC_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define m_HSYNC_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define m_IDI_WHOLE_FRM_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define m_VOP_WHOLE_FRM_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define v_VSYNC_ENABLE(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define v_HSYNC_ENABLE(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define v_IDI_WHOLE_FRM_EN(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define v_VOP_WHOLE_FRM_EN(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CSITX_SYS_CTRL3 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define m_NON_CONTINUES_MODE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define m_CONT_MODE_CLK_SET BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define m_CONT_MODE_CLK_CLR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define v_NON_CONTINUES_MODE_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define v_CONT_MODE_CLK_SET(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define v_CONT_MODE_CLK_CLR(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CSITX_TIMING_CTRL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSITX_TIMING_VPW_NUM 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CSITX_TIMING_VBP_NUM 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CSITX_TIMING_VFP_NUM 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CSITX_TIMING_HPW_PADDING_NUM 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CSITX_VOP_PATH_CTRL 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define m_VOP_PATH_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define m_VOP_DT_USERDEFINE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define m_VOP_VC_USERDEFINE_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define m_VOP_WC_USERDEFINE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define m_PIXEL_FORMAT GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define m_VOP_DT_USERDEFINE GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define m_VOP_VC_USERDEFINE GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define m_VOP_WC_USERDEFINE GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define v_VOP_PATH_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define v_VOP_DT_USERDEFINE_EN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define v_VOP_VC_USERDEFINE_EN(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define v_VOP_WC_USERDEFINE_EN(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define v_PIXEL_FORMAT(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define v_VOP_DT_USERDEFINE(x) (((x) & 0x3f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define v_VOP_VC_USERDEFINE(x) (((x) & 0x3) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define v_VOP_WC_USERDEFINE(x) (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CSITX_VOP_PATH_PKT_CTRL 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define m_VOP_LINE_PADDING_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define m_VOP_LINE_PADDING_NUM GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define m_VOP_PKT_PADDING_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define m_VOP_WC_ACTIVE GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define v_VOP_LINE_PADDING_EN(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define v_VOP_LINE_PADDING_NUM(x) (((x) & 0x7) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define v_VOP_PKT_PADDING_EN(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define v_VOP_WC_ACTIVE(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CSITX_BYPASS_PATH_CTRL 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define m_BYPASS_PATH_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define m_BYPASS_DT_USERDEFINE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define m_BYPASS_VC_USERDEFINE_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define m_BYPASS_WC_USERDEFINE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define m_CAM_FORMAT GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define m_BYPASS_DT_USERDEFINE GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define m_BYPASS_VC_USERDEFINE GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define m_BYPASS_WC_USERDEFINE GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define v_BYPASS_PATH_EN(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define v_BYPASS_DT_USERDEFINE_EN(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define v_BYPASS_VC_USERDEFINE_EN(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define v_BYPASS_WC_USERDEFINE_EN(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define v_CAM_FORMAT(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define v_BYPASS_DT_USERDEFINE(x) (((x) & 0x3f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define v_BYPASS_VC_USERDEFINE(x) (((x) & 0x3) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define v_BYPASS_WC_USERDEFINE(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CSITX_BYPASS_PATH_PKT_CTRL 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define m_BYPASS_LINE_PADDING_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define m_BYPASS_LINE_PADDING_NUM GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define m_BYPASS_PKT_PADDING_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define m_BYPASS_WC_ACTIVE GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define v_BYPASS_LINE_PADDING_EN(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define v_BYPASS_LINE_PADDING_NUM(x) (((x) & 0x7) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define v_BYPASS_PKT_PADDING_EN(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define v_BYPASS_WC_ACTIVE(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CSITX_STATUS0 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CSITX_STATUS1 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define m_DPHY_PLL_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define m_STOPSTATE_CLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define m_STOPSTATE_LANE GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PHY_STOPSTATELANE (m_STOPSTATE_CLK | m_STOPSTATE_LANE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CSITX_STATUS2 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CSITX_LINE_FLAG_NUM 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CSITX_INTR_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define m_INTR_MASK GENMASK(26, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define m_FRM_ST_RX BIT(0 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define m_FRM_END_RX BIT(1 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define m_LINE_END_TX BIT(2 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define m_FRM_ST_TX BIT(3 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define m_FRM_END_TX BIT(4 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define m_LINE_END_RX BIT(5 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define m_LINE_FLAG0 BIT(6 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define m_LINE_FLAG1 BIT(7 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define m_STOP_STATE BIT(8 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define m_PLL_LOCK BIT(9 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define m_CSITX_IDLE BIT(10 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define v_FRM_ST_RX(x) (((x) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define v_FRM_END_RX(x) (((x) & 0x1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define v_LINE_END_TX(x) (((x) & 0x1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define v_FRM_ST_TX(x) (((x) & 0x1) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define v_FRM_END_TX(x) (((x) & 0x1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define v_LINE_END_RX(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define v_LINE_FLAG0(x) (((x) & 0x1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define v_LINE_FLAG1(x) (((x) & 0x1) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define v_STOP_STATE(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define v_PLL_LOCK(x) (((x) & 0x1) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define v_CSITX_IDLE(x) (((x) & 0x1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CSITX_INTR_CLR 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CSITX_INTR_STATUS 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CSITX_INTR_RAW_STATUS 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CSITX_ERR_INTR_EN 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define m_ERR_INTR_EN GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define m_ERR_INTR_MASK GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define m_IDI_HDR_FIFO_OVERFLOW BIT(0 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define m_IDI_HDR_FIFO_UNDERFLOW BIT(1 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define m_IDI_PLD_FIFO_OVERFLOW BIT(2 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define m_IDI_PLD_FIFO_UNDERFLOW BIT(3 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define m_HDR_FIFO_OVERFLOW BIT(4 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define m_HDR_FIFO_UNDERFLOW BIT(5 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define m_PLD_FIFO_OVERFLOW BIT(6 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define m_PLD_FIFO_UNDERFLOW BIT(7 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define m_OUTBUFFER_OVERFLOW BIT(8 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define m_OUTBUFFER_UNDERFLOW BIT(9 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define m_TX_TXREADYHS_OVERFLOW BIT(10 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define m_TX_TXREADYHS_UNDERFLOW BIT(11 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CSITX_ERR_INTR_CLR 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CSITX_ERR_INTR_STATUS 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CSITX_ERR_INTR_RAW_STATUS 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CSITX_ULPS_CTRL 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CSITX_LPDT_CTRL 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CSITX_LPDT_DATA 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CSITX_DPHY_CTRL 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define m_CSITX_ENABLE_PHY GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define v_CSITX_ENABLE_PHY(x) (((x) & 0x1f) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CSITX_DPHY_PPI_CTRL 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CSITX_DPHY_TEST_CTRL 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CSITX_DPHY_ERROR 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CSITX_DPHY_SCAN_CTRL 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CSITX_DPHY_SCANIN 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CSITX_DPHY_SCANOUT 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CSITX_DPHY_BIST 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MIPI_CSI_FMT_RAW8 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MIPI_CSI_FMT_RAW10 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PHY_STATUS_TIMEOUT_US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMD_PKT_STATUS_TIMEOUT_US 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RK_CSI_TX_MAX_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum soc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) RK1808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) enum csi_path_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) VOP_PATH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) BYPASS_PATH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum grf_reg_fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DPIUPDATECFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DPISHUTDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DPICOLORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) VOPSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) TURNREQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TURNDISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FORCETXSTOPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FORCERXMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ENABLE_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MASTERSLAVEZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ENABLECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) BASEDIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DPHY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) TXSKEWCALHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MAX_FIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct rockchip_mipi_csi_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const u32 *csi0_grf_reg_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const u32 *csi1_grf_reg_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long max_bit_rate_per_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum soc_type soc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) const char * const *rsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int rsts_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct mipi_dphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* SNPS PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk *cfg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u16 input_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u16 feedback_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Non-SNPS PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct clk *hs_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct rockchip_mipi_csi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct drm_encoder encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct device_node *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mipi_dsi_host dsi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct mipi_dphy dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct reset_control *tx_rsts[RK_CSI_TX_MAX_RESET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void __iomem *test_code_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 *regsbak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 regs_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int lane_mbps; /* per lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct drm_display_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 path_mode; /* vop path or bypass path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct drm_property *csi_tx_path_property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const struct rockchip_mipi_csi_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum rockchip_mipi_csi_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DSI_COMMAND_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DSI_VIDEO_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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